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INSTRUCTION
MANUAL
THEORY OF OPERATION
Digilal
Multimeter
Models 172A.173A
common.
BT403
is
connected
to
the
inverting
input
of
U401 through
fuse
<403 and
-,
resistor
~408.
When the
voltage
of
BT403 drops
below
the
comparator
threshold,
the
comparator
output
switches
positive,
turning
on the
low battery
indicator.
2)
BT402.
For detecting
a low voltage
condition
of
BT402,
a divider
consisting
of
R411 and R412,
and a NPN transistor
(Q404)
is
used
along
with
the
comparator.
The emitter
of
Q404 is connected
to
the
regulated
-15
volts,
and
its
base
level
is
set
by the
divider
connected
between
common and ET402 through
fuse
F402.
With
the
voltage
of
BT402 at
-19.2
volts,
the
base-emitter
junction
of
Q404
is
reverse
biased
by approx
imately
I volt.
When the
voltage
drops
below
approximately
-17.1
volts,
Q404 is
turne
on,
dropping
the
inverting
input
of
U401 below
the
threshold
voltage
and the
low batte
indicator
is
turned
on by the
output
of
U401.
3)
BT401.
Low voltage
detection
of
ET401
is
similar
to
that
described
for
BT402.
with
the
exception
that
when Q405 is
turned
on the
threshold
voltage
of
U4OI
is
raised
above
the
+8.4
volts
supplied
by BT401.
The result
is
the
same.
The output
of
U401
switches
positive,
turning
on the
low battery
indiiator.
4)
It
should
be noted
that
the
switching
levels
described
above
can vary
slightly,
be=se
of
the
i5% tolerance
of
the
regulated
power
supplies
in the
OHM.
5-8.
MODEL 1722 DIGITAL
INTERFACE.
a.
Overall
Block
Diagram.
As shown
in Figure
5-18,
Serial
data
from
the
DHM and
its
associated
clock
lines
are
first
isolated.
Bidirectional
data
line
SERDAT is
then
sDlit
Output
data
OOWNOAT goes
to
the
output
register
block
where
it
is converted
to parallel
form
and then
to
the
output
buffers.
The clock
lines
go to
the
control
block
which
decides
where
the
data
is going,
out
or
in,
and also
generates
-the
flag.
Control
input
data
and strobes
are
first
buffered
by the
input
buffer
block.
The strobes
go to
the
output
buffer
to gate
the
outputs.
The control.
data
inputs
go to
the
input
register
and control
block
where
they
are
converted
from
parallel
to serial
form
and sent
to
the
isolation
block.
The
input
register
and control
block
also
decides,
based
on control
data
input,
whether
there
is
to
be an output
update.
Power
isolation
for
the
1722 is
provided
by transformer
TIDOI
which
is
powered
by a secondary
winding
of
the
DMH power
transformer.
b.
Siqnal
Isolation.
(See
Schematic
27902E).
The bidirectional
data
line
(SERDAT)
B
the
two clock
lines
(SERCLK and
INCLK),
each
drive
an emitter
follower
(Ql035,
QlO37
or
QlO36)
whose
load
is
an LED in
its
respective
opto-isolator
(UIOIV,
UlO21
and UlO20).
The outputs
of
these
opto-isolators
are
pulled
up by Rl009,
RI012
and R1009,
respective1
~1018
is
driven
by Q1034
in a similar
manner
to
the
three
opto-isolators
just
mentioned,
and
its
output
pullup
is on the
DMM mainframe.
c.
power
SUDDIV.
Low voltage
ac from
the
secondary
of
the
DMM transformer
is
supplie
via
pins
B and C on J1001.
Switching
for
the
power
for
TIOOI,
provided
at
J1003
Pins
A.
and B, comes via
the
DMM mainframe
through
its
Power
ON switch.
The secondary
of
TIOOI
is
rectified,
filtered
and run
through
an integrated
circuit
(+5V
regulator
TRIDOI)
whose
output
is
filtered
by ClOl5,
ClOO2,
ClOO3,
C1004,
ClO14.
The core
of
TIOOI
is
connected
to chassis
ground
by a green
wire
to a screw
on the
DMH mainframe
or
transforr
Also
common mode filtering
is
performed
by ~1008
and cl006
connected
between
output
low
and chassis
ground.
d.
Control
Block.
UPCLK,
the
isolated
form
of
INCLK,
is
run
to
the
t-rigger
input
of
El017
timer.
A buffered
version
of
UPCLK is
also
run
via
diode
gate
CR1002
to the
threshhold
input
of
UlOl7.
UlDl7
is such
that
its
output
will
go high
when a falling
edge
goes
into
trigger.
A filter
made up of
RI007
and Cl008
will
tw
to charqe.
however
since
this
threshhold
is
clamped
low
through
diode
CR1002.
it
will
not
be able
to
time
5-2:
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