Mt1379 - Cambridge Audio DVD53 Service Manual

Speci f i c ati o ns are subj e ct to change wi t hout noti c e

8.2 MT1379

n
Super Integration DVD player single chip
§
Servo controller and data channel processing
§
MPEG-1/MPEG-2/JPEG video decoding
§
Dolby AC-3/DTS/DVD -Audio audio decoding
§
Unified track buffer and A/V decoding buffer
§
Video processing for scaling and video quality
enhancement
§
OSD & Sub-picture decoding
§
Built-in clock generator
§
Built-in TV encoder
§
Built-in progressive video output
§
Video input port and audio/SPDIF input port
n
Speed Performance on Servo and Decoding
§
DVD-ROM up to 8XS
§
CD-ROM up to 24XS
§
Built-in a frequency programmable clock to
and RSPC Decoder to optimize the performance
over power
n
Channel Data Processor
§
Provides interface with analog front-end
processor
§
Analog data slicer for small jitter capability
§
Built-in high performance data PLL for chann el
data demodulation
§
EFM/EFM+ data demodulation
§
Enhanced channel data frame sync protection &
DVD-ROM sector sync protection
n
Servo Control and Spindle Motor Control
§
Programmable frequency error gain and phase
error gain of spindle PLL to control spindle motor
on CLV and CAV mode
§
Provide a varipitch speed control for CLV and CAV
mode
§
Built-in ADCs and DACs for digital servo control
§
Provide 2 general PWM
Progressive Scan DVD Player Combo Chip
§
Tray control can be PWM output or digital output
§
Built-in DSP for digital servo control
n
Host Micro controller
§
Built-in 8032 micro controller
§
Built-in internal 373 and 8-bit programmable
lower address port
§
1024-bytes on-chip RAM
§
Up to 2M bytes FLASH-programming interface
§
Supports 5/3.3-Volt. FLASH interface
§
Supports power-down mode
§
Supports additional serial port
n
DVD-ROM/CD-ROM Decoding Logic
§
Supports CD-ROM Mode 1, CD-ROM XA Mode 2
Form 1, CD-ROM XA Mode 2 Form 2, and CD-DA
µ
P
formats
§
High-speed ECC logic capable of correcting one
error per each P-codeword or Q-codeword
§
Automatic sector Mode and Form detection
§
Automatic sector Header verification
§
8-bit counter for decode completion check
§
Programmable descrambling and error
correction schemes
§
Automatically repeated error corrections
§
8-bit C2 Pointer counter
§
Decoder Error Notification Interrupt that signals
various decoder errors
§
Provide error correction acceleration
n
Buffer Memory Controller
§
Supports 16Mb/32Mb/64Mb/128Mb SDRAM
§
Supports 16-bit/32-bit SDRAM data bus interface
§
Build in a DRAM interface programmable clock to
optimize the DRAM performance
§
Provide the self-refresh mode SDRAM
§
Programmable DRAM access cycle and refresh
19
MT1379