Advanced Chipset Features - MSI 915GM User Manual

M S-7177 M -ATX M ainboard

Advanced Chipset Features

MSI Reminds You...
Change these settings only if you are familiar with the chipset.
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [By SPD] enables DRAM timings and the
following related items to be determined by BIOS based on the configurations on the
SPD. Selecting [Manual] lets users configure the DRAM timings and the following
related items manually. Setting options: [Manual], [By SPD].
CAS Latency Time
This controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it. Settings: [Auto], [2], [2.5],
[3]. [2] increases the system performance the most while [3] provides the most stable
performance.
DRAM RAS# to CAS# Delay
W hen DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance. Setting options: [Auto], [2], [3], [4], [5].
DRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS) to be allowed
to precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data.
This item applies only when synchronous DRAM is installed in the system. Setting
options: [Auto], [2], [3], [4], [5].
3-12