Silicon Laboratories Si4432 Manual
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Silicon Laboratories Si4432 Manual

Ism transceiver
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Si4432 ISM T
Features
Frequency Range = 240–930 MHz
Sensitivity = –118 dBm
+20 dBm Max Output Power
Configurable +11 to +20 dBm

Low Power Consumption
18.5 mA receive

27 mA @ +11 dBm transmit

Data Rate = 1 to 128 kbps
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Wake-on-radio
Auto-frequency calibration (AFC)
Applications
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Tire Pressure monitoring
Wireless PC peripherals
Description
Silicon Laboratories' Si4432 highly integrated, single chip wireless ISM
transceiver is part of the EZRadioPRO™ family. The EZRadioPRO family includes
a complete line of transmitters, receivers, and transceivers allowing the RF
system designer to choose the optimal wireless part for their application.
The Si4432 offers advanced radio features including continuous frequency
coverage from 240–930 MHz and adjustable output power of up to +20 dBm. The
Si4432's high level of integration offers reduced BOM cost while simplifying the
overall system design. The extremely low receive sensitivity (–118 dBm) coupled
with industry leading +20 dBm output power ensures extended range and
improved link performance. Built-in antenna diversity and support for frequency
hopping can be used to further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble
detection reduce overall current consumption and allow the use of lower-cost
system MCUs. An integrated temperature sensor, general purpose ADC, power-
on-reset (POR), and GPIOs further reduce overall system cost and size.
The Si4432's digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased flexibility and performance. This digital architecture simplifies
system design while allowing for the use of lower-end MCUs. The direct digital
transmit modulation and automatic PA power ramping ensure precise transmit
modulation and reduced spectral spreading ensuring compliance with FCC and
ETSI regulations.
Preliminary Rev. 0.4 6/09
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Downloaded from
Elcodis.com
electronic components distributor
RANSCEIVER
Antenna diversity and TR switch
control
Configurable packet structure
Preamble detector
TX and RX 64 byte FIFOs
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
FSK, GFSK, and OOK modulation
Low BOM
Power-on-reset (POR)
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Tag readers
Copyright © 2009 by Silicon Laboratories
Si4432
Ordering Information:
See page 156.
Pin Assignments
Si4432
20
19 18 17
16
VDD_RF
1
15
TX
2
14
RXp
3
13
RXn
4
12
VR_IF
5
11
6
7
8
9
10
Metal
Paddle
Patents pending
SCLK
SDI
SDO
VDD_DIG
NC
Si4432

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Summary of Contents for Silicon Laboratories Si4432

  • Page 1 The Si4432 offers advanced radio features including continuous frequency coverage from 240–930 MHz and adjustable output power of up to +20 dBm. The Si4432’s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (–118 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance.
  • Page 2 Si4432 Functional Block Diagram RC 32K OSC VDD_RF RF LDO PLL LDO VCO LDO 30M XTAL Temp Sensor 8Bit Digital Logic TXMOD Delta Sigma Modulator SCLK ANTDIV TXRXSW SPI, & Controller PA_RAMP VDD_DIG PWR_CTRL Digital Modem AGC Control Low Power...

  • Page 3: Table Of Contents

    Si4432 ABLE O F ONTENTS Section Page 1. Electrical Specifications ...........8 1.1.
  • Page 4 13. Pin Descriptions: Si4432 ........
  • Page 5 Si4432 I S T OF IGURES Figure 1. +20 dBm Application with Antenna Diversity and FHSS..........17 Figure 2. SPI Timing........................19 Figure 3. SPI Timing—READ Mode ..................20 Figure 4. SPI Timing—Burst Write Mode .................. 20 Figure 5. SPI Timing—Burst Read Mode .................. 20 Figure 6.
  • Page 6 Si4432 Figure 44. RX LNA Matching..................... 83 Figure 45. TX Matching and Filtering for Different Bands ............84 Figure 46. QFN-20 Package ....................157 Figure 47. PCB Land Pattern ....................158 Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...
  • Page 7 Si4432 I S T OF ABLES 1 ..........................8 Table 1. DC Characteristics 1 ..................9 Table 2. Synthesizer AC Electrical Characteristics Table 3. Receiver AC Electrical Characteristics ..............10 1 ................... 11 Table 4. Transmitter AC Electrical Characteristics 1 ......................12 Table 5. Auxiliary Block Specifications Table 6.

  • Page 8: Electrical Specifications

    Si4432 1. Electrical Specifications Table 1. DC Characteristics Parameter Symbol Conditions Max Units Supply Voltage Range Power Saving Modes — — RC Oscillator, Main Digital Regulator, Shutdown and Low Power Digital Regulator OFF — — Low Power Digital Regulator ON (Register values retained)

  • Page 9: Table 2. Synthesizer Ac Electrical Characteristics 1

    Si4432 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Conditions Units Synthesizer Frequency Low Band — SYNTH-LB Range High Band — SYNTH-HB Synthesizer Frequency Low Band — 156.25 — RES-LB Resolution High Band — 312.5 — RES-HB Reference Frequency —...

  • Page 10: Table 3. Receiver Ac Electrical Characteristics

    Si4432 Table 3. Receiver AC Electrical Characteristics Parameter Symbol Conditions Units RX Frequency Low Band — SYNTH-LB Range High Band — SYNTH-HB RX Sensitivity (BER < 0.1%) — –118 — RX_2 (2 kbps, GFSK, BT = 0.5, f = 5 kHz) (BER <...

  • Page 11: Table 4. Transmitter Ac Electrical Characteristics 1

    Si4432 Table 4. Transmitter AC Electrical Characteristics Parameter Symbol Conditions Units TX Frequency Low Band — SYNTH-LB Range High Band — SYNTH-HB FSK Modulation Data Rate — kbps OOK Modulation Data — kbps Rate Modulation Deviation Δf Production tests maximum ±0.625...

  • Page 12: Table 5. Auxiliary Block Specifications 1

    Si4432 Table 5. Auxiliary Block Specifications Parameter Symbol Conditions Units Temperature Sensor When calibrated using temp — — °C Accuracy sensor offset register Temperature Sensor — — mV/°C Sensitivity Low Battery Detector — — Resolution Low Battery Detector — —...

  • Page 13: Table 6. Digital Io Specifications (Sdo, Sdi, Sclk, Nsel, And Nirq)

    Si4432 Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Symbol Conditions Units Rise Time 0.1 x V to 0.9 x V = 5 pF — — RISE Fall Time 0.9 x V to 0.1 x V = 5 pF —...

  • Page 14: Table 8. Absolute Maximum Ratings

    Si4432 Table 8. Absolute Maximum Ratings Parameter Value Unit to GND –0.3, +3.6 to GND on TX Output Pin –0.3, +8.0 Voltage on Digital Control Inputs –0.3, V + 0.3 Voltage on Analog Inputs –0.3, V + 0.3 RX Input Power C...

  • Page 15: Definition Of Test Conditions

    External reference signal (XOUT) = 1.0 V at 30 MHz, centered around 0.8 VDC Production test schematic (unless noted otherwise) All RF input and output levels referred to the pins of the Si4432 (not the RF module) Extreme Test Conditions: = –40 to +85 °C = +1.8 to +3.6 VDC...

  • Page 16: Functional Description

    2. Functional Description and +20 dBm in 3 dB steps. The PA is single-ended to The Si4432 is a 100% CMOS ISM wireless transceiver allow for easy antenna matching and low BOM cost. with continuous frequency tuning over the complete The PA incorporates automatic ramp-up and ramp- 240–930 MHz band.

  • Page 17: Figure 1. +20 Dbm Application With Antenna Diversity And Fhss

    Si4432 Supply Voltage 30 MHz 100 p 100 n VDD_RF SCLK TR & ANT-DIV Switch Microcontroller Si4432 VDD_D VR_IF Programmable load capacitors for X1 are integrated. R1, L1–L5 and C1–C4 values depend on frequency band, antenna impedance, output power, and supply voltage range.

  • Page 18: Operating Modes

    Table 9 summarizes the modes of operation of the Si4432. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode.

  • Page 19: Controller Interface

    Select high period To read back data from the Si4432, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register.

  • Page 20: Figure 3. Spi Timing-Read Mode

    Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be latched into the Si4432 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5.

  • Page 21: Operating Mode Control

    Si4432 3.2. Operating Mode Control There are four primary states in the Si4432 radio state machine: SHUTDOWN, IDLE, TX, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs.
  • Page 22 Si4432 3.2.1. Shutdown State The shutdown state is the lowest current consumption state of the device with nominally less than 10 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states except the SHUTDOWN state.
  • Page 23 Si4432 3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA to prevent unwanted spectral splatter.

  • Page 24: Interrupts

    Si4432 3.3. Interrupts The Si4432 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur.

  • Page 25: System Timing

    Si4432 3.5. System Timing The system timing for TX and RX modes is shown in Figures 8 and 7. The timing is shown transitioning from STANDBY mode to TX mode and going automatically through the built-in sequencer of required steps. If a small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device.

  • Page 26: Figure 8. Rx Timing

    Si4432 XTAL Settling RX Packet Time ~1ms Figure 8. RX Timing Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 27: Frequency Control

    In order to receive or transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the Si4432. Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3 order) ΔΣ...

  • Page 28: Table 12. Frequency Band Selection

    Si4432 Table 12. Frequency Band Selection fb[4:0] Value Frequency Band hbsel=0 hbsel=1 240–249.9 MHz 480–499.9 MHz 250–259.9 MHz 500–519.9 MHz 260–269.9 MHz 520–539.9 MHz 270–279.9 MHz 540–559.9 MHz 280–289.9 MHz 560–579.9 MHz 290–299.9 MHz 580–599.9 MHz 300–309.9 MHz 600–619.9 MHz 310–319.9 MHz...
  • Page 29 3.6.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4432, it is often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register.

  • Page 30: Figure 9. Frequency Deviation

    Si4432 carrier Time Figure 9. Frequency Deviation The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency;...

  • Page 31: Figure 10. Sensitivity At 1% Per Vs. Carrier Frequency Offset

    Si4432 3.6.5. Frequency Offset Adjustment When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency.
  • Page 32 Si4432 The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in “Register 1Dh. AFC Loop Gearshift Override,” on page 109), the Frequency Offset shows the results of the AFC algorithm for the current receive slot. When selecting the preamble length, the length needs to be long enough to settle the AFC.
  • Page 33 Si4432 3.6.7. TX Data Rate Generator The data rate is configurable between 1–128 kbps. For data rates below 30 kbps the ”txdtrtscale” bit in register 70h should be set to 1. When higher data rates are used this bit should be set to 0.

  • Page 34: Modulation Options

    4. Modulation Options 4.1. Modulation Type The Si4432 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 11 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps.

  • Page 35: Modulation Data Source

    4.2. Modulation Data Source The Si4432 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. Furthermore, in Direct Mode, the TX modulation data may be obtained from several different input pins.

  • Page 36: Pn9 Mode

    Si4432 4.5. PN9 Mode In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having to load/provide data.

  • Page 37: Figure 14. Fifo Mode Example

    Si4432 nIRQ nSEL FIFO mode utilizing internal packet SCLK VDD_RF handler. Data loaded/read through SPI MOSI into FIFO. C MISO Matching VDD_DIG GPIO configuration VR_IF Not Utilized Figure 14. FIFO Mode Example Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 38: Internal Functional Blocks

    Si4432 5. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240–930 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages.

  • Page 39: Synthesizer

    Si4432 The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is enabled, the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow the receiver to settle.

  • Page 40: Power Amplifier

    5.7. Power Amplifier The Si4432 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between +11 to +20 dBm. The output power is programmable in 3 dB steps through the txpow[1:0] field in "Register 6Dh. TX Power".

  • Page 41: Crystal Oscillator

    5.8. Crystal Oscillator The Si4432 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components.

  • Page 42: Data Handling And Packet Handler

    Si4432 6. Data Handling and Packet Handler 6.1. RX and TX FIFOs Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 16. "Register 7Fh. FIFO Access" is used to access both FIFOs. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)"...

  • Page 43: Packet Configuration

    The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the Si4432 and therefore also reduces the required computational power of the microcontroller.

  • Page 44: Packet Handler Tx Mode

    Si4432 6.3. Packet Handler TX Mode If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to ready mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the chip to re-enter TX mode Figure 18 provides an example transaction where the packet length is set to three bytes.

  • Page 45: Figure 21. Multiple Packets In Rx With Crc Or Header Error

    Si4432 Initial state PK 1 OK PK 2 OK PK 3 PK 4 OK ERROR RX FIFO Addr. RX FIFO Addr. RX FIFO Addr. RX FIFO Addr. RX FIFO Addr. Write Pointer Data Data Data Data Write Pointer Data Data...

  • Page 46: Table 14. Packet Handler Registers

    Si4432 Table 14. Packet Handler Registers Function/Description POR Def. Data Access Control enpacrx lsbfrst crcdonly enpactx encrc crc[1] crc[0] EzMAC status rxcrc1 pksrch pkrx pkvalid crcerror pktx pksent — Header Control 1 bcen[3] enbcast[2] enbcast[1] enbcast[0] hdch[3] hdch[2] hdch[1] hdch[0]...

  • Page 47: Data Whitening, Manchester Encoding, And Crc

    Figure 22. Operation of Data Whitening, Manchester Encoding, and CRC 6.6. Preamble Detector The Si4432 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in “6.2.

  • Page 48: Invalid Preamble Detector

    6.9. TX Retransmission and Auto TX The Si4432 is capable of automatically retransmitting the last packet in the FIFO if no additional packets were loaded into the TX FIFO. Automatic Retransmission is achieved by entering the TX state with the txon bit set. This feature is useful for Beacon transmission or when retransmission is required due to the absence of a valid acknowledgement.

  • Page 49: Rx Modem Configuration

    Si4432 7. RX Modem Configuration 7.1. Modem Settings for FSK and GFSK The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 620 to 2.6 kHz. The data-rate, modulation index, and bandwidth are set via registers 1C–25. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb).
  • Page 50 Si4432 7.1.1. Advanced FSK and GFSK Settings In nearly all cases, the information in Table 16, “RX Modem Configurations for FSK and GFSK,” on page 49 can be used to determine the required FSK and GFSK modem parameters. The section includes a more detailed discussion of the various modem parameters to allow for experienced designers to further configure the modem performance.

  • Page 51: Table 17. Filter Bandwidth Parameters

    Si4432 Table 17. Filter Bandwidth Parameters ndec_exp dwn3_bypass filset BW [kHz] ndec_exp dwn3_bypass filset [kHz] 1C-[6:4] 1C-[7] 1C-[3:0] 1C-[6:4] 1C-[7] 1C-[3:0] 41.7 45.2 47.9 56.2 64.1 69.2 75.2 83.2 90.0 95.3 112.1 127.9 137.9 142.8 167.8 10.6 181.1 11.5 191.5 12.1...

  • Page 52: Modem Settings For Ook

    7.2. Modem Settings for OOK The Si4432 is configured for OOK mode by setting the modtyp[1:0] field to OOK in "Register 71h. Modulation Mode Control 2". In OOK mode, the following parameters can be configured: data rate, manchester coding, channel filter bandwidth, and the clock recovery oversampling rate.

  • Page 53: Table 19. Ndec[2:0] Settings

    Si4432 Table 19. ndec[2:0] Settings Rb(1+ enmanch) [kbps] ndec[2:0] The clock recovery oversampling rate is set via rxosr[10:0] in "Register 20h. Clock Recovery Oversampling Rate" and "Register 21h. Clock Recovery Offset 2". ndec_exp and dwn3_bypass together with the receive data rate (Rb) are used to calculate rxosr: ...

  • Page 54: Table 20. Rx Modem Configuration For Ook With Manchester Disabled

    Si4432 Table 20. RX Modem Configuration for OOK with Manchester Disabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters Register Values RX BW dwn3_bypass ndec_exp[2:0] filset[3:0] rxosr[10:0] ncoff[19:0] crgain[10:0] [kbps] [kHz] 20,21h 21,22,23h 24,25h 09D49 09D49 0346E 0346E...

  • Page 55: Auxiliary Functions

    8. Auxiliary Functions 8.1. Smart Reset The Si4432 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances.

  • Page 56: Microcontroller Clock

    If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the Si4432 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock.

  • Page 57: General Purpose Adc

    Si4432 8.3. General Purpose ADC An 8-bit SAR ADC is integrated onto the chip for general purpose use, as well as for digitizing the temperature sensor reading. “Register 0Fh. ADC Configuration,” on page 103 must be configured depending on the use of the GP ADC before use.

  • Page 58: Figure 25. Adc Differential Input Example-Bridge Sensor

    Si4432 8.3.1. ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this configuration will utilize two GPIO pins. The supply source of the bridge and chip should be the same to eliminate the measuring error caused by battery discharging.

  • Page 59: Figure 26. Adc Differential Input Offset For Sensor Offset Coarse Compensation

    Si4432 The differential offset can be coarse compensated by the adcoffs[3:0] bits found in "Register 11h. ADC Value". Fine compensation should be done by the microcontroller software. The main reason for the offset compensation is to shift the negative offset voltage of the bridge sensor to the positive differential voltage range. This is essential as the differential input mode is unipolar.

  • Page 60: Temperature Sensor

    Si4432 8.4. Temperature Sensor An analog temperature sensor is integrated into the chip. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus.

  • Page 61: Figure 27. Temperature Ranges Using Adc8

    Si4432 Temperature Measurement with ADC8 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 3 Temperature [Celsius] Figure 27. Temperature Ranges using ADC8 Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 62: Low Battery Detector

    Si4432 8.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller.

  • Page 63: Wake-Up Timer

    Si4432 8.6. Wake-Up Timer The chip contains an integrated wake-up timer which periodically wakes the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode.

  • Page 64: Figure 28. Wut Interrupt And Wut Operation

    Si4432 Interrupt Enable enwut=1 (Reg 06h) WUT Period GPIOX=00001 nIRQ SPI Interrupt Read Chip State Sleep Ready Sleep Ready Sleep Ready Sleep Current Consumption 600n 600n 600n Interrupt Enable enwut =0 (Reg 06h) WUT Period GPIOX=00001 nIRQ SPI Interrupt Read...

  • Page 65: Low Duty Cycle Mode

    Si4432 8.7. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period.

  • Page 66: Gpio Configuration

    Si4432 8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low.

  • Page 67: Figure 30. Gpio Usage Examples

    Si4432 GPIO Configuration A Supply Voltage 30 MHz 100 p 100 n VDD_RF SCLK Microcontroller Si4432 VDD_D TRSW VR_IF Sensor GPIO Configuration B Supply Voltage 30 MHz 100 p 100 n VDD_RF SCLK Microcontroller Si4432 VDD_D VR_IF Micrcontroller CLK Data Input/Output Data CLK Figure 30.

  • Page 68: Antenna-Diversity

    Si4432 8.9. Antenna-Diversity To mitigate the problem of frequency-selective fading due to multi-path propagation, some transceiver systems use a scheme known as Antenna Diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet.

  • Page 69: Rssi And Clear Channel Assessment

    Si4432 8.11. RSSI and Clear Channel Assessment The RSSI (Received Signal Strength Indicator) signal is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 31 demonstrates the relationship between input power level and RSSI value.

  • Page 70: Reference Design

    Si4432 9. Reference Design Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 71: Table 25. Split Rf I/Os Bill Of Materials

    Si4432 Table 25. Split RF I/Os Bill of Materials Part Value Device Package Description Capacitor 0603 Murata GRM18 series 33pF Capacitor 0603 Murata GRM18 series 100pF Capacitor 0603 Murata GRM18 series 100nF Capacitor 0603 Murata GRM18 series 2.2uF POLARIZED CAPACITOR...

  • Page 72: Figure 33. Common Tx/Rx Connector With Rf Switch-Schematic

    Si4432 Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 73: Table 26. Common Tx/Rx Connector Bill Of Materials

    Si4432 Table 26. Common TX/RX Connector Bill of Materials Part Value Device Package Description vertical SMA connector BU-SMA-V SMA connector, vertical Capacitor 0603 Murata GRM18 series C_M2 Capacitor 0603 Murata GRM18 series C_M3 Capacitor 0603 Murata GRM18 series Capacitor 0603...

  • Page 74: Figure 34. Antenna Diversity Reference Design-Schematic

    Si4432 Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 75: Table 27. Antenna Diversity Bill Of Materials

    Si4432 Table 27. Antenna Diversity Bill of Materials Part Value Device Package Description ANT1 90° BU-SMA-RADIAL BU-SMA-V SMA female connector, vertical ANT2 90° BU-SMA-RADIAL BU-SMA-V SMA female connector, vertical Capacitor 0603 Murata GRM18 33pF C-USC0603K 0603 Murata GRM18 100pF C-USC0603K...

  • Page 76: Measurement Results

    Si4432 10. Measurement Results Sensitivity vs. Data Rate Measured at RX SMA Connector Input -100 dBm -102 dBm -104 dBm -106 dBm -108 dBm -110 dBm -112 dBm -114 dBm -116 dBm -118 dBm -120 dBm 1 kbps 10 kbps...

  • Page 77: Figure 36. Receiver Selectivity

    Si4432 Adjacent Channel Selectivity at 50 kbps Measured at RX SMA Connector Input 10 dB AGC Enabled 0 dB -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00...

  • Page 78: Figure 37. Tx Output Power Vs. Vdd Voltage

    Si4432 Output Power vs. VDD 20.00 dBm 18.00 dBm 16.00 dBm 14.00 dBm 12.00 dBm 10.00 dBm 8.00 dBm 6.00 dBm 4.00 dBm 2.00 dBm 0.00 dBm 2.0 V 2.5 V 3.0 V 3.5 V VDD Voltage Figure 37. TX Output Power vs. VDD Voltage Output Power vs Temp 19.0 dBm...

  • Page 79: Figure 39. Tx Modulation (40 Kbps, 20 Khz Deviation)

    Si4432 Si4432 Figure 39. TX Modulation (40 kbps, 20 kHz Deviation) Figure 40. TX Unmodulated Spectrum (917 MHz) Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 80: Figure 41. Tx Modulated Spectrum (917 Mhz, 40 Kbps, 20 Khz Deviation, Gfsk)

    Si4432 Figure 41. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) Si4432 Figure 42. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 81: Figure 43. Synthesizer Phase Noise (Vcocurr = 11)

    Si4432 Figure 43. Synthesizer Phase Noise (VCOCURR = 11) Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...

  • Page 82: Application Notes

    Si4432 11. Application Notes This section offers a brief introduction to a number of application related topics. Further recommended reading can be found in our related application notes at http://www.silabs.com. 11.1. Crystal Selection The recommended crystal parameters are given in Table 28.

  • Page 83: Matching Network Design

    The output voltage swing of the Si4432 PA depends on the supply voltage to the device, the antenna matching network, and the antenna impedance. The output voltage swing of the Si4432 at the TX pin must be kept below 6.5 V to ensure long-term reliability of the device. Depending on the maximum supply voltage to the device and the impedance presented to the chip by the antenna and matching network, a limiting resistor may be installed above pull-up inductor L1, with its value adjusted to ensure safe operation.

  • Page 84: Figure 45. Tx Matching And Filtering For Different Bands

    The following table provides recommended values of the limiting resistor R versus operating voltage and antenna return loss for some common V and return loss combinations. For operation outside of these ranges, consult with Silicon Laboratories’ applications support team. RDC (  ) Max V Antenna Return Loss (dB) >6...

  • Page 85: Reference Material

    Si4432 12. Reference Material 12.1. Complete Register Table and Descriptions Table 30. Register Descriptions Function/Desc Data Default Device Type dt[4] dt[3] dt[2] dt[1] dt[0] 00111 Device Version vc[4] vc[3] vc[2] vc[1] vc[0] — Device Status ffovfl ffunfl rxffem headerr freqerr...
  • Page 86 Si4432 Table 30. Register Descriptions (Continued) Function/Desc Data Default Header Enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] Header Enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] Header Enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2]...
  • Page 87 Si4432 Register 00h. Device Type Code (DT) Reserved dt[4:0] Name Type Reset value = 00001000 Name Function Reserved Reserved. dt[4:0] Device Type Code. EZRadioPRO: 01000 Register 01h. Version Code (VC) Reserved vc[4:0] Name Type Reset value = xxxxxxxx Name Function Reserved Reserved.
  • Page 88 Si4432 Register 02h. Device Status ffovfl ffunfl rxffem headerr freqerr lockdet cps[1:0] Name Type Reset value = xxxxxxxx Name Function ffovfl RX/TX FIFO Overflow Status. ffunfl RX/TX FIFO Underflow Status. rxffem RX FIFO Empty Status. headerr Header Error Status. Indicates if the received packet has a header check error.
  • Page 89 Si4432 Register 03h. Interrupt/Status 1 ifferr itxffafull ixtffaem irxffafull iext ipksent ipkvalid icrerror Name Type Reset value = xxxxxxxx Name Function ifferr FIFO Underflow/Overflow Error. When set to 1 the TX or RX FIFO has overflowed or underflowed. itxffafull TX FIFO Almost Full.

  • Page 90: Table 31. Interrupt Or Status 1 Bit Set/Clear Description

    Si4432 Table 31. Interrupt or Status 1 Bit Set/Clear Description Status Set/Clear Conditions Name ifferr Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset. itxffafull Set when the number of bytes written to TX FIFO is greater than the Almost Full threshold.
  • Page 91 Si4432 Register 04h. Interrupt/Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor Name Type Reset value = xxxxxxxx Name Function iswdet Sync Word Detected. When a sync word is detected this bit will be set to 1. ipreaval Valid Preamble Detected.

  • Page 92: Table 33. Interrupt Or Status 2 Bit Set/Clear Description

    Si4432 Table 33. Interrupt or Status 2 Bit Set/Clear Description Status Set/Clear Conditions Name iswdet Goes high once the Sync Word is detected. Goes low once we are done receiving the cur- rent packet. ipreaval Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for the sync times-out.
  • Page 93 Si4432 Register 05h. Interrupt Enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror Name Type Reset value = 00000000 Name Function enfferr Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled. entxffafull Enable TX FIFO Almost Full.
  • Page 94 Si4432 Register 06h. Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor Name Type Reset value = 00000011 Name Function enswdet Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled. enpreaval Enable Valid Preamble Detected.
  • Page 95 Si4432 Register 07h. Operating Mode and Function Control 1 swres enlbd enwt x32ksel txon rxon pllon xton Name Type Reset value = 00000001 Name Function swres Software Register Reset Bit. This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register.
  • Page 96 Si4432 Register 08h. Operating Mode and Function Control 2 antdiv[2:0] rxmpk autotx enldm ffclrrx ffclrtx Name Type Reset value = 00000000 Name Function antdiv[2:0] Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
  • Page 97 Si4432 Register 09h. 30 MHz Crystal Oscillator Load Capacitance xtalshft xlc[6:0] Name Type Reset value = 01000000 Name Function xtalshft Direct Control to Analog. xlc[6:0] Tuning Capacitance for the 30 MHz XTAL. Preliminary Rev. 0.4 Downloaded from Elcodis.com electronic components distributor...
  • Page 98 Si4432 Register 0Ah. Microcontroller Output Clock Reserved clkt[1:0] enlfc mclk[2:0] Name Type Reset value = xx000110 Name Function Reserved Reserved. clkt[1:0] Clock Tail. If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to complete its operation.
  • Page 99 Si4432 Register 0Bh. GPIO Configuration 0 gpiodrv0[1:0] pup0 gpio0[4:0] Name Type Reset value = 00000000 Name Function gpiodrv0[1:0] GPIO Driving Capability Setting. pup0 Pullup Resistor Enable on GPIO0. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input.
  • Page 100 Si4432 Register 0Ch. GPIO Configuration 1 gpiodrv1[1:0] pup1 gpio1[4:0] Name Type Reset value = 00000000 Name Function gpiodrv1[1:0] GPIO Driving Capability Setting. pup1 Pullup Resistor Enable on GPIO1. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input.
  • Page 101 Si4432 Register 0Dh. GPIO Configuration 2 gpiodrv2[1:0] pup2 gpio2[4:0] Name Type Reset value = 00000000 Name Function gpiodrv2[1:0] GPIO Driving Capability Setting. pup2 Pullup Resistor Enable on GPIO2. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input.
  • Page 102 Si4432 Register 0Eh. I/O Port Configuration Reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 Name Type Reset value = 00000000 Name Function Reserved Reserved. extitst[2] External Interrupt Status. If the GPIO2 is programmed to be external interrupt sources then the status can be read here.
  • Page 103 Si4432 Register 0Fh. ADC Configuration adcstart/ adcsel[2:0] adcref[1:0] adcgain[1:0] Name adcdone Type Reset value = 00000000 Name Function adcstart/adc- ADC Measurement Start Bit. done Reading this bit gives 1 if the ADC measurement cycle has been finished. adcsel[2:0] ADC Input Source Selection.
  • Page 104 Si4432 Register 10h. ADC Sensor Amplifier Offset Reserved adcoffs[3:0] Name Type Reset value = xxxx0000 Name Function Reserved Reserved. adcoffs[3:0] ADC Sensor Amplifier Offset*. *Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD / 1000; MSB = adcoffs[3] = Sign bit.
  • Page 105 Si4432 Register 12h. Temperature Sensor Calibration tsrange[1:0] entsoffs entstrim tstrim[3:0] Name Type Reset value = 00100000 Name Function tsrange[1:0] Temperature Sensor Range Selection. (FS range is 0..1024 mV) –40 C .. 64 C (full operating range), with 0.5 C resolution (1 LSB in the 8-bit ADC) –40 C ..
  • Page 106 Si4432 Register 14h. Wake-Up Timer Period 1 Reserved wtr[3:0] wtd[1:0] Name Type Reset value = xx000000 Name Function Reserved Reserved. wtr[3:0] Wake Up Timer Exponent (R) Value*. wtd[3:0] Wake Up Timer Exponent (D) Value*. *Note: The period of the wake-up timer can be calculated as T = (32 x M x 2 ) / 32.768 ms.
  • Page 107 Si4432 Register 17h. Wake-Up Timer Value 1 wtm[15:8] Name Type Reset value = xxxxxxxx Name Function wtm[15:8] Wake Up Timer Current Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as T = (32 x M x 2 ) / 32.768 ms.
  • Page 108 Si4432 Register 1Ah. Low Battery Detector Threshold Reserved lbdt[4:0] Name Type Reset value = xxx10100 Name Function Reserved Reserved. lbdt[4:0] Low Battery Detector Threshold. This threshold is compared to Battery Voltage Level. If the Battery Voltage is less than the threshold the Low Battery Interrupt is set.
  • Page 109 Si4432 Register 1Ch. IF Filter Bandwidth dwn3_bypass ndec_exp[2:0] filset[3:0] Name Type Reset value = 00000001 Name Function dwn3_bypass Bypass Decimator by 3 (if set). ndec_exp[2:0] IF Filter Decimation Rates. filset[3:0] IF Filter Coefficient Sets. Defaults are for Rb = 40 kbps and Fd = 20 kHz so Bw = 80 kHz.
  • Page 110 Si4432 Register 1Eh. AFC Timing Control Reserved shwait[2:0] lgwait[2:0] Name Type Reset value = xx001000 Name Function Reserved Reserved. shwait[2:0] Short Wait Periods after AFC Correction. Used before preamble is detected. Short wait = (RegValue + 1) x 2T If set to 0 then no AFC correction will occur before preamble detect, i.e.
  • Page 111 Si4432 Register 1Fh. Clock Recovery Gearshift Override Reserved rxready crfast[2:0] crslow[2:0] Name Type Reset value = 00000011 Name Function Reserved Reserved. rxready Improves Receiver Noise Immunity when in Direct Mode. It is recommended to set this bit after preamble is detected. When in FIFO mode this bit should be set to “0”...
  • Page 112 Si4432 Register 20h. Clock Recovery Oversampling Rate rxosr[7:0] Name Type Reset value = 01100100 Name Function rxosr[7:0] Oversampling Rate. 3 LSBs are the fraction, default = 0110 0100 = 12.5 clock cycles per data bit The offset can be calculated as follows: ...
  • Page 113 Si4432 Register 22h. Clock Recovery Offset 1 ncoff[15:8] Name Type Reset value = 01000111 Name Function ncoff[15:8] NCO Offset. See formula above Register 23h. Clock Recovery Offset 0 ncoff[7:0] Name Type Reset value = 10101110 Name Function ncoff[7:0] NCO Offset.
  • Page 114 Si4432 Register 25h. Clock Recovery Timing Loop Gain 0 crgain[7:0] Name Type Reset value = 10001111 Name Function crgain[7:0] Clock Recovery Timing Loop Gain. Register 26h. Received Signal Strength Indicator rssi[7:0] Name Type Reset value = 00000000 Name Function rssi[7:0] Received Signal Strength Indicator Value.
  • Page 115 Si4432 Register 28h. Antenna Diversity 1 adrssi[7:0] Name Type Reset value = 00000000 Name Function adrssi[7:0] Measured RSSI Value on Antenna 1. Register 29h. Antenna Diversity 2 adrssi2[7:0] Name Type Reset value = 00000000 Name Function adrssi2[7:0] Measured RSSI Value on Antenna 2.
  • Page 116 Si4432 Register 30h. Data Access Control enpacrx lsbfrst crcdonly Reserved enpactx encrc crc[1:0] Name Type Reset value = 10001101 Name Function enpacrx Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled.
  • Page 117 Si4432 ® Register 31h. EZMAC Status Reserved rxcrc1 pksrch pkrx pkvalid crcerror pktx pksent Name Type Reset value = 00000000 Name Function Reserved Reserved. rxcrc1 If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error.
  • Page 118 Si4432 Register 32h. Header Control 1 bcen[3:0] hdch[3:0] Name Type Reset value = 00001100 Name Function bcen[3:0] Broadcast Address (FFh) Check Enable. If it is enabled together with Header Byte Check then the header check is OK if the incoming header byte equals with the appropriate check byte or FFh). One hot encoding.
  • Page 119 Si4432 Register 33h. Header Control 2 Reserved hdlen[2:0] fixpklen synclen[1:0] prealen[8] Name Type Reset value = 00100010 Name Function Reserved Reserved. hdlen[2:0] Header Length. Length of header used if packet handler is enabled for TX/RX (enpactx/rx). Headers are transmitted/received in descending order.
  • Page 120 Si4432 Register 34h. Preamble Length prealen[7:0] Name Type Reset value = 00001000 Name Function prealen[7:0] Preamble Length. The value in the prealen[8:0] register corresponds to the number of nibbles (4 bits) in the packet. For example prealen[8:0] = ‘000001000’ corresponds to a preamble length of 32 bits (8 x 4bits) or 4 bytes.
  • Page 121 Si4432 Register 37h. Synchronization Word 2 sync[23:16] Name Type Reset value = 11010100 Name Function sync[23:16] Synchronization Word 2. byte of the synchronization word. Register 38h. Synchronization Word 1 sync[15:8] Name Type Reset value = 00000000 Name Function sync[15:8] Synchronization Word 1.
  • Page 122 Si4432 Register 3Ah. Transmit Header 3 txhd[31:24] Name Type Reset value = 00000000 Name Function txhd[31:24] Transmit Header 3. byte of the header to be transmitted. Register 3Bh. Transmit Header 2 txhd[23:16] Name Type Reset value = 00000000 Name Function txhd[23:16] Transmit Header 2.
  • Page 123 Si4432 Register 3Dh. Transmit Header 0 txhd[7:0] Name Type Reset value = 00000000 Name Function txhd[7:0] Transmit Header 0. byte of the header to be transmitted. Register 3Eh. Packet Length pklen[7:0] Name Type Reset value = 00000000 Name Function pklen[7:0] Packet Length.
  • Page 124 Si4432 Register 3Fh. Check Header 3 chhd[31:24] Name Type Reset value = 00000000 Name Function chhd[31:24] Check Header 3. byte of the check header. Register 40h. Check Header 2 chhd[23:16] Name Type Reset value = 00000000 Name Function chhd[23:16] Check Header 2.
  • Page 125 Si4432 Register 42h. Check Header 0 chhd[7:0] Name Type Reset value = 00000000 Name Function chhd[7:0] Check Header 0. byte of the check header. Header Enable bytes 3 to 0 control which bits of the Check Header bytes are checked against the corresponding bits in the Received Header.
  • Page 126 Si4432 Register 45h. Header Enable 1 hden[15:8] Name Type Reset value = 00000000 Name Function hden[15:8] Header Enable 1. byte of the check header. Register 46h. Header Enable 0 hden[7:0] Name Type Reset value = 00000000 Name Function hden[7:0] Header Enable 0.
  • Page 127 Si4432 Register 48h. Received Header 2 rxhd[23:16] Name Type Reset value = 00000000 Name Function rxhd[23:16] Received Header 2. byte of the received header. Register 49h. Received Header 1 rxhd[15:8] Name Type Reset value = 00000000 Name Function rxhd[15:8] Received Header 1.
  • Page 128 Si4432 Register 4Bh. Received Packet Length rxplen[7:0] Name Type Reset value = 11111111 Name Function rxplen[7:0] Length Byte of the Received Packet during fixpklen = 0 . (Specifies the number of Data bytes in the last received packet) This will be relevant ONLY if fixpklen (address 33h, bit[3]) is low during the receive time.

  • Page 129: Table 35. Internal Analog Signals Available On The Analog Test Bus

    Si4432 Table 35. Internal Analog Signals Available on the Analog Test Bus atb[4:0] GPIOx GPIOx MixIp MixIn MixQp MixQn PGA_Ip PGA_In PGA_QP PGA_Qn ADC_vcm ADC_vcmb ADC_ipoly10u ADC_ref ADC_Refdac_p ADC_Refdac_n ADC_ipoly10 ADC_ipoly10 ADC_Res1Ip ADC_Res1In ADC_Res1Qp ADC_Res1Qn Reserved Reserved Reserved Reserved Reserved...

  • Page 130: Table 36. Internal Digital Signals Available On The Digital Test Bus

    Si4432 Register 51h. Digital Test Bus Select Reserved ensctest dtb[5:0] Name Type Reset value = 00000000 Name Function Reserved Reserved. ensctest Scan Test Enable. When set to 1 then GPIO0 will be the ScanEn input. dtb[5:0] Digital Test Bus. GPIO must be configured to Digital Test Mux output.
  • Page 131 Si4432 Table 36. Internal Digital Signals Available on the Digital Test Bus (Continued) dtb[4:0] GPIO0 Signal GPIO1 Signal GPIO2 Signal chip ready: READY state pll_en PLL enable: TUNE state tx_en TX enable: TX state ts_en temperature sensor enable auto_tx_on automatic TX ON...
  • Page 132 Si4432 Register 52h. TX Ramp Control Reserved txmod[2:0] ldoramp[1:0] txramp[1:0] Name Type Reset value = 00100000 Name Function Reserved Reserved txmod[2:0] TX Modulation Delay. The time delay between PA enable and the beginning of the TX modulation to allow for PA ramp-up.
  • Page 133 Si4432 The total settling time (cold start) of the PLL after the calibration can be calculated as T Register 53h. PLL Tune Time pllts[4:0] pllt0 Name Type Reset value = 01010010 Name Function pllts[4:0] PLL Soft Settling Time (T This register will set the settling time for the PLL from a previous locked frequency in Tune mode.
  • Page 134 Si4432 Register 55h. Calibration Control Reserved xtalstarthalf adccaldone enrcfcal rccal vcocaldp vcocal skipvco Name Type Reset value = x0x00100 Name Function Reserved Reserved. xtalstarthalf If Set, the Xtal Wake Time Period is Halved. adccaldone Delta-sigma ADC Calibration Done. Reading this bit gives 1 if the calibration process has been finished.
  • Page 135 Si4432 Register 56h. Modem Test bcrfbyp slicfbyp dttype afcpol Reserved refclksel refclkinv iqswitch Name Type Reset value = 00000000 Name Function bcrfbyp If set, BCR phase compensation will be bypassed. slicfbyp If set, slicer phase compensation will be bypassed. dttype Dithering Type.
  • Page 136 Si4432 Register 58h. Charge Pump Current Trimming/Override cpcurr[1:0] cpcorrov cporr[4:0] Name Type Reset value = 100xxxxx Name Function cpcurr[1:0] Charge Pump Current (Gain Setting). Changing these bits will change the BW of the PLL. The default setting is adequate for all data rates.
  • Page 137 Si4432 Register 5Ah. VCO Current Trimming txcurboosten vcocorrov vcocorr[3:0] vcocur[1:0] Name Type Reset value = 10000011 Name Function txcurboosten If this is Set, then vcocur = 11 during TX Mode and VCO CAL followed by TX. vcocorrov VCO Current Correction Override.
  • Page 138 Si4432 Register 5Ch. Synthesizer Test dsmdt vcotype enoloop dsmod dsorder[1:0] dsrstmode dsrst Name Type Reset value = 0x001110 Name Function dsmdt Enable DSM Dithering. If low, dithering is disabled. vcotype VCO Type. 0: basic, constant K 1: single varactor, changing K enoloop Open Loop Mode Enable.
  • Page 139 Si4432 Register 5Dh. Block Enable Override 1 enmix enina enpga enpa enbf5 endv32 enbf12 enmx2 Name Type Reset value = 00000000 Name Function enmix Mixer Enable Override. enlna LNA Enable Override. enpga PGA Enable Override. enpa Power Amplifier Enable Override.
  • Page 140 Si4432 Register 5Fh. Block Enable Override 3 enfrdv endv31 endv2 endv1p5 dvbshunt envco encp enbg Name Type Reset value = 00000000 Name Function enfrdv Fractional Divider Enable Override. endv31 Divider 3_1 Enable Override. endv2 Divider 2 Enable Override. endv1p5 Divider 1.5 (div-by-1.5) Enable Override.
  • Page 141 Si4432 Register 61h. Channel Filter Coefficient Value Reserved chfilval[5:0] Name Type Reset value = 00000000 Name Function Reserved Reserved. chfilval[5:0] Filter Coefficient Value in the Look-up Table Addressed by the chfiladd[3:0]. Register 62h. Crystal Oscillator/Power-on-Reset Control pwst[2:0] clkhyst enbias2x enamp2x...
  • Page 142 Si4432 Register 63h. RC Oscillator Coarse Calibration/Override rccov rcc[6:0] Name Type Reset value = 00000000 Name Function rccov RC Oscillator Coarse Calibration Override. When rccov = 0 the internal Coarse Calibration results may be viewed by reading the rcccal register. When rccov = 1 the Coarse results may be overridden externally through the SPI by writing to the rcccal register.
  • Page 143 Si4432 Register 65h. LDO Control Override enspor enbias envcoldo enifldo enrfldo enpllldo endigldo endigpwdn Name Type Reset value = 10000001 Name Function enspor Smart POR Enable. enbias Bias Enable. envcoldo VCO LDO Enable. enifldo IF LDO Enable. enrfldo RF LDO Enable.
  • Page 144 Si4432 Register 67h. Delta-Sigma ADC Tuning 1 adcrst enrefdac enadc adctuneovr adctune[3:0] Name Type Reset value = 00011101 Name Function adcrst Delta-Sigma ADC Reset. enrefdac Delta-Sigma ADC Reference DAC Enable Override. enadc Delta-Sigma ADC Enable Override. adctuneovr Resonator RC Calibration Value Override Enable.
  • Page 145 Si4432 Register 69h. AGC Override 1 Reserved agcen lnagain pga[3:0] Name Type Reset value = 00100000 Name Function Reserved Reserved. agcen Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0].
  • Page 146 Si4432 Register 6Bh. GFSK FIR Filter Coefficient Address Reserved firadd[2:0] Name Type Reset value = xxxxx000 Name Function Reserved Reserved. firadd[2:0] GFSK FIR Filter Coefficient Look-up Table Address. The address for Gaussian filter coefficients used in the TX path. The default GFSK set- ting is for BT = 0.5.
  • Page 147 Si4432 Register 6Dh. TX Power Reserved txpow[2] txpow[1:0] Name Type Reset value = xxxxxx11 Name Function Reserved Reserved. txpow[2] TX Output Power. This bit is used in 4x31 output power programming. txpow[1:0] TX Output Power. The output power is configurable from +20 dBm to +11 dBm in ~3 dBm steps.
  • Page 148 Si4432 Register 6Fh. TX Data Rate 0 txdr[7:0] Name Type Reset value = 00001101 Name Function txdr[7:0] Data Rate Lower Byte. See formula above. Defaults = 40 kbps. Register 70h. Modulation Mode Control 1 Reserved txdtrtscale enphpwdn manppol enmaninv enmanch...
  • Page 149 Si4432 Register 71h. Modulation Mode Control 2 trclk[1:0] dtmod[1:0] eninv fd[8] modtyp[1:0] Name Type Reset value = 00000000 Name Function trclk[1:0] TX Data Clock Configuration. No TX Data CLK is available (asynchronous mode – Can only work with modula- tions FSK or OOK).
  • Page 150 Si4432 Register 72h. Frequency Deviation fd[7:0] Name Type Reset value = 00100000 Name Function fd[7:0] Frequency Deviation Setting. See formula above. Note: It's recommended to use modulation index of 1 or higher (maximum allowable modulation index is 32). The modulation...
  • Page 151 Si4432 Register 74h. Frequency Offset 2 Reserved fo[9:8] Name Type Reset value = 00000000 Name Function Reserved Reserved. fo[9:8] Upper Bits of the Frequency Offset Setting. fo[9] is the sign bit. The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0].
  • Page 152 Si4432 Register 76h. Nominal Carrier Frequency fc[15:8] Name Type Reset value = 10111011 Name Function fc[15:8] Nominal Carrier Frequency Setting. See formula above. Register 77h. Nominal Carrier Frequency fc[7:0] Name Type Reset value = 10000000 Name Function fc[7:0] Nominal Carrier Frequency Setting.
  • Page 153 Si4432 Register 7Ah. Frequency Hopping Step Size fhs[7:0] Name Type Reset value = 00000000 Name Function fhs[7:0] Frequency Hopping Step Size in 10 kHz Increments. See formula for the nominal carrier frequency at "Register 76h. Nominal Carrier Fre- quency". Register 7Ch. TX FIFO Control 1...
  • Page 154 Si4432 Register 7Eh. RX FIFO Control Reserved rxafthr[5:0] Name Type Reset value = 00110111 Name Function Reserved Reserved. rxafthr[5:0] RX FIFO Almost Full Threshold. Register 7Fh. FIFO Access fifod[7:0] Name Type Reset value = NA Name Function fifod[7:0] FIFO Data.

  • Page 155: Pin Descriptions: Si4432

    SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. PADDLE_GND The exposed metal paddle on the bottom of the Si4432 supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4432.

  • Page 156: Ordering Information

    Si4432 14. Ordering Information Part Description Package Operating Number* Type Temperature Si4432-V2-FM ISM Transceiver QFN-20 –40 to 85 °C Pb-free *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.

  • Page 157: Package Outline

    Si4432 15. Package Outline Figure 46 illustrates the package details for the Si4432. Table 37 lists the values for the dimensions shown in the illustration. Figure 46. QFN-20 Package Table 37. Package Dimensions Dimension 0.80 0.85 0.90 0.00 0.02 0.05 0.18...

  • Page 158: Pcb Land Pattern

    Si4432 16. PCB Land Pattern Figure 47 illustrates the PCB land pattern details for the Si4432. Table 38 lists the values for the dimensions shown in the illustration. Figure 47. PCB Land Pattern Table 38. PCB Land Pattern Dimensions Dimension Dimension 3.90...

  • Page 159: Document Change List

    Revision 0.1 to Revision 0.2 Reformatted all registers.  Updated “9. Reference Design”.  Added "13. Pin Descriptions: Si4432" on page 155.  Added "14. Ordering Information" on page 156.  Revision 0.2 to Revision 0.3 Updated Pinout and Figures to reflect pin 6 and 11 ...

  • Page 160: Contact Information

    Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.

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