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Silicon Laboratories SI4421 Product Manual
Silicon Laboratories SI4421 Product Manual

Silicon Laboratories SI4421 Product Manual

Universal ism band fsk transceiver

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Si4421 Universal ISM Band
FSK Transceiver
DESCRIPTION
Silicon Labs' Si4421 is a single chip, low power, multi-channel FSK
transceiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 433, 868 and 915 MHz bands.
The Si4421 transceiver is a part of Silicon Labs' EZRadio
line, which produces a flexible, low cost, and highly integrated solution
that does not require production alignments. The chip is a complete
analog RF and baseband transceiver including a multi-band PLL
synthesizer with PA, LNA, I/Q down converter mixers, baseband filters
and amplifiers, and an I/Q demodulator. All required RF functions are
integrated. Only an external crystal and bypass filtering are needed for
operation.
The Si4421 features a completely integrated PLL for easy RF design,
and its rapid settling time allows for fast frequency-hopping, bypassing
multipath fading and interference to achieve robust wireless links. The
PLL's high resolution allows the usage of multiple channels in any of
the bands. The receiver baseband bandwidth (BW) is programmable to
accommodate various deviation, data rate and crystal tolerance
requirements. The transceiver employs the Zero-IF approach with I/Q
demodulation. Consequently, no external components (except crystal
and decoupling) are needed in most applications.
The Si4421 dramatically reduces the load on the microcontroller with
the integrated digital data processing features: data filtering, clock
recovery, data pattern recognition, integrated FIFO and TX data
register. The automatic frequency control (AFC) feature allows the use
of a low accuracy (low cost) crystal. To minimize the system cost, the
Si4421 can provide a clock signal for the microcontroller, avoiding the
need for two crystals.
For low power applications, the Si4421 supports low duty cycle
operation based on the internal wake-up timer.
FUNCTIONAL BLOCK DIAGRAM
MIX
I
AMP
RF1
13
LNA
RF2 12
MIX
Q
AMP
PA
PLL & I/Q VCO
with cal.
RF Parts
BB Amp/Filt./Limiter
WTM
CLK div
Xosc
with cal.
Low Power parts
8
9
CLK
XTL /
REF
Si4421-DS rev 2.4r 0708
OC
I/Q
Self cal.
DEMOD
OC
RSSI
COMP
DQD
AFC
LBD
Controller
15
1
2
3
4
5
10
16
ARSSI
SDI
SCK
nSEL SDO
nIRQ
nRES
nINT /
VDI
product
TM
This document refers to Si4421-IC rev A1.
See www.silabs.com/integration for any applicable errata.
FEATURES
 Fully integrated (low BOM, easy design-in)
 No alignment required in production
 Fast-settling, programmable, high-resolution PLL synthesizer
 Fast frequency-hopping capability
 High bit rate (up to 115.2 kbps in digital mode and 256 kbps
in analog mode)
 Direct differential antenna input/output
 Integrated power amplifier
 Programmable TX frequency deviation (15 to 240 kHz)
 Programmable RX baseband bandwidth (67 to 400 kHz)
 Analog and digital RSSI outputs
 Automatic frequency control (AFC)
 Data quality detection (DQD)
 Internal data filtering and clock recovery
 RX synchron pattern recognition
 SPI compatible serial control interface
 Clock and reset signals for microcontroller
 16-bit RX Data FIFO
 Two 8-bit TX data registers
 Low power duty cycle mode
 Standard 10 MHz crystal reference with on-chip tuning
 Wake-up timer
 2.2 to 3.8 V supply voltage
DCLK /
 Low power consumption
7
CFIL /
FFIT /
clk
 Low standby current (0.3 A)
Data Filt
FSK /
data
CLK Rec
6
DATA /
nFFS
 Compact 16 pin TSSOP package
 Supports very short packets (down to 3 bytes)
FIFO
 Excellent temperature stability of the RF parameters
 Good adjacent channel rejection/blocking
Data processing units
TYPICAL APPLICATIONS
Bias
 Home security and alarm
 Remote control, keyless entry
11
14
 Wireless keyboard/mouse and other PC peripherals
VSS VDD
 Toy controls
 Remote keyless entry
 Tire pressure monitoring
 Telemetry
 Personal/patient data logging
 Remote automatic meter reading
Si4421
PIN ASSIGNMENT
See back page for ordering information.
1
www.silabs.com

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Summary of Contents for Silicon Laboratories SI4421

  • Page 1 Si4421 Universal ISM Band FSK Transceiver DESCRIPTION Silicon Labs’ Si4421 is a single chip, low power, multi-channel FSK transceiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 433, 868 and 915 MHz bands.
  • Page 2 DETAILED FEATURE-LEVEL DESCRIPTION The Si4421 FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application.
  • Page 3: Crystal Oscillator

     Higher data rate  Inexpensive crystals Crystal Oscillator The Si4421 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.
  • Page 4 Positive supply voltage ARSSI Analog RSSI output nINT Interrupt input (active low) Valid data indicator output Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver. Si4421...
  • Page 5 Internal Pin Connections Name Internal connection 1.5k nSEL nIRQ DATA nFFS DLCK CFIL FFIT Name Internal connection nRES ARSSI nINT Si4421...
  • Page 6 Si4421 PIN6 Logic Diagram (FSK / DATA / nFFS) PIN10 Logic Diagram (nRES I/O) * Note: These pins can be left floating.
  • Page 7: Typical Application

    The el and ef bits can be found in the Configuration Setting Command on page 15. Bit el enables the internal TX data register. Bit ef enables the FIFO mode. Typical application with FIFO usage 2.2u (optional) nSEL Si4421 nIRQ (optional)* nFFS (optional)* FFIT...
  • Page 8: General Device Specifications

    Note 2: The actual voltage on RF1 and RF2 pins can be lower than the current V Units -0.5 -0.5 +0.5 -0.5 +1.5 (Note 1) 1000 Units -1.5 (Note 2) +1.5 but cannot exceed 7 V. but never should go below 1.2 V. Si4421...
  • Page 9: Electrical Specification

    915 MHz band All blocks disabled Crystal oscillator on (Note 1) Programmable in 0.1 V steps 2.25 0.7·V = 0 V = 3.8 V = 2 mA = -2 mA Si4421 Units µA µA µA 3.75 ± 3 0.3·V µA µA...
  • Page 10 When input signal level lower than -54 dBm and greater than -100 dBm Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit C = 4.7 nF ARRSI Si4421 Units 439.75 879.51 929.27 µs µs Units 115.2...
  • Page 11 ± 10% After V has reached 90% of final value (Note 8) Crystal oscillator must be enabled to ensure proper calibration at the start up. (Note 9) 15 pF pure capacitive load Si4421 Units -17.5 dBc/Hz -103 kbps kbps Units µs...
  • Page 12 Note 4: See reference design with 50 Ohm Matching Network (page 39) for details Note 5: See reference design with Resonant PCB Antenna (BIFA) on page 41 for details Note 6: Optimal antenna admittance/impedance: Si4421 [mS] antenna 2 – j5.9 433 MHz 1.2 - j11.9...
  • Page 13: Control Interface

    Data hold time (SCK rising edge to SDI transition) Data delay time Timing Diagram nSEL BIT 15 BIT 14 BIT 13 FFIT FFOV BIT 8 BIT 7 BIT 1 AT S OFFS(0) Si4421 Minimum value [ns] BIT 0 FIFO OUT...
  • Page 14: Control Commands

    CC77h B8AAh E196h C80Eh C000h 0000h Si4421 Related control bits el, ef, b1 to b0, x3 to x0 er, ebb, et, es, ex, eb, ew, dc f11 to f0 cs, r6 to r0 p16, d1 to d0, i2 to i0, g1 to g0, r2...
  • Page 15 It is important to note that leaving blocks unnecessary turned on can increase the current consumption thus decreasing the battery life. Related blocks RF front end, baseband, synthesizer, crystal oscillator Baseband Power amplifier, synthesizer, crystal oscillator Synthesizer Crystal oscillator Low battery detector Wake-up timer Clock output buffer Si4421 8008h Crystal Load Capacitance [pF] 10.0 … 15.5 16.0 8208h...
  • Page 16 (supposing that both the er and et bits are cleared), the interrupts have no effect on it. enable power amplifier enable VCO and RF synthesizer start TX TX latch clear TX latch enable Crystal crystal oscillator oscillator Digital signal processing clock and data out Si4421 enable RF front end enable baseband circuits demod...
  • Page 17 BR/BR < 1/(29 · N Clock recovery in fast mode: BR is the bit rate difference between the transmitter and the receiver. N Function of pin 16 Interrupt input VDI output Si4421 A680h Band [MHz] PLL Frequency Step 2.5 kHz 5.0 kHz 7.5 kHz...
  • Page 18 Note: For the optimal bandwidth settings at different data rates see the table on page 37. Response Fast Medium Slow Always on SEL0 SEL1 FAST MEDIUM SLOW LOGIC HIGH er * R/S FF Note: * For details see the Power Management Command BW [kHz] Reserved Reserved Si4421...
  • Page 19 Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO cannot be used. Gain relative to maximum [dB] RSSI setth -103 Reserved Reserved Filter Type Digital filter Analog RC filter 19.2 8.2 nF 6.8 nF 3.3 nF 1.5 nF Si4421 C22Ch 38.4 57.6 115.2 680 pF 270 pF 150 pF 100 pF...
  • Page 20 Synchron Pattern Command (page 21). Bit 2 (al): Set the input of the FIFO fill start condition: ) / bit rate offset Byte1 Byte0 (POR) Synchron Pattern (Byte1+Byte0) FIFO fill start condition Synchron pattern Always fill Si4421 CA80h 2DD4h...
  • Page 21 Operation mode Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the f only during receiving (VDI=high) offset Keep the f value independently from the state of the VDI signal offset Si4421 CED4h B000h C4F7h...
  • Page 22 The main benefits of the automatic frequency control: cheap crystal can be used, the temperature or aging drift will not cause range loss and no production alignment needed. 433 MHz bands: 2.5 kHz to -16 f 868 MHz band: 5 kHz to -8 f 915 MHz band: 7.5 kHz to -4 f Si4421...
  • Page 23 (See: Antenna Application Note: IA ISM-AN1) mp=0 and FSK=0 mp=1 and FSK=1 Note: FSK represents the value of the actual data bit Si4421 9800h mp=0 and FSK=1 mp=1 and FSK=0...
  • Page 24 Note: Alternately the transmit register can be directly accessed by nFFS (pin6). Selected µC CLK frequency 5 or 10 MHz (recommended) 3.3 MHz 2.5 MHz or less Phase noise at 1MHz offset [dBc/Hz] 86.2 -107 -102 TX BYTE1 TX BYTE2 Si4421 ddit CC77h B8AAh TX BYTEn...
  • Page 25 There is an application proposal on page 26. The Si4421 is configured to work in FIFO mode. The chip periodically wakes up and switches to receiving mode. If valid FSK data received, the chip sends an interrupt to the microcontroller and continues filling the RX FIFO.
  • Page 26 Clock divider configuration: The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command (page 15). Clock Output Frequency [MHz] 1.25 1.66 3.33 Si4421 C000h of the detector:...
  • Page 27 (page 21). The AFC offset value (OFFS bits in the status word) is represented as a two’s complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step (see the Frequency Setting Command on page 17). Function Si4421 0000h...
  • Page 28: Interrupt Handling

     EXT: both the nIRQ pin and status bit follow the level of the nINT pin  LBD: the nIRQ pin can be released by the reading the status, but the status bit will remain active while the VDD is below the threshold. Si4421...
  • Page 29 Also, the Si4421 will not go to low current sleep mode if any interrupt remains active regardless to the state of the ex (enable crystal oscillator) bit in the Power Management Command (page 15).
  • Page 30 PA turn off should be delayed for at least 16 bits time. The clock source of the microcontroller (if the clock is not supplied by the Si4421) should be stable enough over temperature and voltage to ensure this minimum delay under all operating circumstances.
  • Page 31 FIFO OUT FO+1 FO+2 FO+3 FO+4 FFIT /4, where f is the crystal oscillator frequency. When the duty-cycle of the Synchron word (Can be network ID) D4h (programmable) 2DD4h (D4 is programmable) Si4421 Payload 4 bit - 1 byte 2 byte...
  • Page 32 CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4421 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps.
  • Page 33 Si4421 RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
  • Page 34: Reset Modes

    (250mV must drop below 250mV in order to trigger a power-on reset Si4421 voltage and the internal ramp...
  • Page 35 Issuing FE00h command will trigger software reset (sensitive reset mode must be enabled). See the Wake-up Timer Command (page 25). Reset threshold voltage (600mV) Reset ramp line (100mV/ms) Reset threshold voltage (600mV) ramp start.. Typical example when a switch-mode line. Follow the manufacturer’s recommendations Si4421 time Reset ramp line (100mV/ms) time...
  • Page 36: Typical Performance Characteristics

    Phase Noise Performance in the 433, 868 and 915 MHz Bands: (Measured under typical conditions: T CW interferer offset from carrier [MHz] 433 MHz 868 MHz 915 MHz = 27 C; V = 2.7 V) Si4421 434 MHz 868 MHz ETSI = 2.7 V...
  • Page 37 =45 kHz =45 kHz -110 -105 -100 -105 -100 9.6 kbps 19.2 kbps BW=67 kHz BW=67 kHz f f =45kHz =45 kHz =45 kHz Si4421 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k...
  • Page 38 Receiver Sensitivity over Ambient Temperature (868 MHz, 2.4 kbps, -100 -103 -106 -109 -112 -115 434 MHz Celsius 868 MHz Celsius Si4421  : 45 kHz, BW: 67 kHz): 2.2V 2.7V 3.3V 3.8V  : 45 kHz, BW: 67 kHz): 2.2V 2.7V 3.3V...
  • Page 39: Reference Designs

    434MHz 868 MHz 0603CS-18NX 0603CS-3N9X 0603CS-18NX 0603CS-3N9X 0603CS-47NX 0603CS-18NX 0603CS-R39X 0603CS-R10X GRM1885C1H1R2CZ01B GRM1885C1H2R7CZ01B GRM1885C1H1R8CZ01B GRM1885C1H470JZ01B GRM1885C1H470JZ01B Si4421 MATCHING_NETWORK CN62 optional * See values in the table C10 [pF] C11 [pF] C3 [pF] 915MHz 0603CS-3N9X 0603CS-3N9X 0603CS-16NX 0603CS-R10X GRM1885C1H1R2CZ01B GRM1885C1H2R7CZ01B GRM1885C1H1R8CZ01B...
  • Page 40 3. The dielectric type should be C0G and the resonant frequency should be similar if components from alternative vendor used. 4. The values are valid for 1.5mm thick FR4 PCB. If thinner board used the capacitor value should be increased (and vice versa) to minimize the level of the second harmonic components. PCB Layout Top View Bottom View Si4421...
  • Page 41 Frequency Dependent Component Values Band C3 [pF] L1 [nH] 868 MHz Dual (868/915 MHz) 47/33 915 MHz NINT/VDI ARSSI NSEL NIRQ 2.2uF DATA FSK/DATA/NFFS DCLK DCLK/CFIL NRES XTL/REF IA4421 100pF Si4421 ARSSI RESET * See values in the table CLKIN...
  • Page 42 Si4421 PCB Layout (Antenna designed for 868/915 MHz band) Top View Bottom View...
  • Page 43: Package Information

    0,22 0,25 0,007 5,00 5,10 0,193 6.40 BSC. 4,40 4,50 0,169 0,60 0,75 0,020 1.00 REF. 12 REF. 12 REF. Si4421 0.25 Detail “A” ” Nom. Max. 0,035 0,041 0,009 0,010 0,197 0,201 0.252 BSC. 0,173 0,177 0,024 0,030 0.39 REF.
  • Page 44: Related Resources

    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2008 Silicon Laboratories, Inc. All rights reserved. Silicon Laboratories is a trademark of Silicon Laboratories, Inc. All other trademarks belong to their respective owners. Si4421...
  • Page 45 Si4421...