Silicon Laboratories Si4432 Transceiver Manuals

Manuals and User Guides for Silicon Laboratories Si4432 Transceiver. We have 1 Silicon Laboratories Si4432 Transceiver manual available for free PDF download: Manual

Silicon Laboratories Si4432 Manual (166 pages)

Brand: Silicon Laboratories | Category: Transceiver | Size: 2 MB

Table of Contents
3
Electrical Specifications
8
Table 1. DC Characteristics
8
Table 2. Synthesizer AC Electrical Characteristics
9
Table 3. Receiver AC Electrical Characteristics
10
Table 4. Transmitter AC Electrical Characteristics
11
Table 5. Auxiliary Block Specifications
12
Table 6. Digital IO Specifications (SDO, SDI, SCLK, Nsel, and Nirq)
13
Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
13
Table 8. Absolute Maximum Ratings
14
Definition of Test Conditions
15
Functional Description
16
Figure 1. +20 Dbm Application with Antenna Diversity and FHSS
17
Operating Modes
18
Table 9. Operating Modes
18
Figure 2. TX Timing
19
Figure 3. RX Timing
19
Controller Interface
20
Serial Peripheral Interface (SPI)
20
Figure 4. SPI Timing
20
Table 10. Serial Interface Timing Parameters
20
Operating Mode Control
21
Figure 5. SPI Timing-READ Mode
21
Figure 6. SPI Timing-Burst Write Mode
21
Figure 7. SPI Timing-Burst Read Mode
21
Figure 8. State Machine Diagram
22
Table 11. Operating Modes
22
Table 12. Frequency Band Selection
27
Figure 9. Sensitivity Vs. Carrier Frequency Offset
30
Modulation Options
32
Modulation Type
32
Modulation Data Source
32
Figure 10. FSK Vs GFSK Spectrums
32
FIFO Mode
33
Direct Mode
33
PN9 Mode
33
Synchronous Vs. Asynchronous
33
Figure 11. Direct Synchronous Mode Example
34
Figure 12. Direct Asynchronous Mode Example
34
Figure 13. FIFO Mode Example
34
Internal Functional Blocks
35
Rx Lna
35
RX I-Q Mixer
35
Programmable Gain Amplifier
35
Adc
35
Digital Modem
35
Synthesizer
36
Power Amplifier
37
Figure 14. PLL Synthesizer Block Diagram
37
Crystal Oscillator
38
Regulators
38
Data Handling and Packet Handler
39
RX and TX Fifos
39
Figure 15. FIFO Thresholds
39
Packet Configuration
40
Packet Handler TX Mode
40
Figure 16. Packet Structure
40
Figure 17. Multiple Packets in TX Packet Handler
40
Packet Handler RX Mode
41
Figure 18. Required RX Packet Structure with Packet Handler Disabled
41
Figure 19. Multiple Packets in RX Packet Handler
41
Figure 20. Multiple Packets in RX with CRC or Header Error
41
Table 13. RX Packet Handler Configuration
42
Table 14. Packet Handler Registers
43
Data Whitening, Manchester Encoding, and CRC
44
Preamble Detector
44
Figure 21. Operation of Data Whitening, Manchester Encoding, and CRC
44
Preamble Length
45
Invalid Preamble Detector
45
Table 15. Minimum Receiver Settling Time
45
TX Retransmission and Auto TX
46
RX Modem Configuration
47
Modem Settings for FSK and GFSK
47
Table 16. RX Modem Configurations for FSK and GFSK
47
Table 17. Filter Bandwidth Parameters
49
Modem Settings for OOK
50
Table 18. Channel Filter Bandwidth Settings
50
Table 19. Ndec[2:0] Settings
51
Table 20. RX Modem Configuration for OOK with Manchester Disabled
52
Table 21. RX Modem Configuration for OOK with Manchester Enabled
52
Auxiliary Functions
53
Smart Reset
53
Figure 22. por Glitch Parameters
53
Table 22. por Parameters
53
Microcontroller Clock
54
General Purpose ADC
55
Figure 23. General Purpose ADC Architecture
55
Figure 24. ADC Differential Input Example-Bridge Sensor
57
Figure 25. ADC Differential Input Offset for Sensor Offset Coarse Compensation
58
Temperature Sensor
59
Figure 26. Temperature Ranges Using ADC8
60
Table 23. Temperature Sensor Range
60
Low Battery Detector
61
Wake-Up Timer
62
Low Duty Cycle Mode
63
Figure 27. WUT Interrupt and WUT Operation
63
Figure 28. Low Duty Cycle Mode
63
GPIO Configuration
64
Figure 29. GPIO Usage Examples
65
Antenna-Diversity
66
Table 24. Antenna Diversity Control
66
TX/RX Switch Control
67
RSSI and Clear Channel Assessment
67
Figure 30. RSSI Value Vs. Input Power
67
Analog and Digital Test Bus
68
Table 25. Analog Test Bus
68
Table 26. Internal Digital Signals Available on the Digital Test Bus
69
Reference Design
70
Figure 31. Split RF I/Os with Separated TX and RX Connectors - Schematic
70
Table 27. Split RF I/Os Bill of Materials
71
Figure 32. Split RF I/Os with Separated TX and RX Connectors - Top
72
Figure 33. Split RF I/Os with Separated TX and RX Connectors - Top Silkscreen
72
Figure 34. Split RF I/Os with Separated TX and RX Connectors - Bottom
73
Figure 35. Common TX/RX Connector with RF Switch - Schematic
74
Table 28. Common TX/RX Connector Bill of Materials
75
Figure 36. Common TX/RX Connector with RF Switch - Top
76
Figure 37. Common TX/RX Connector with RF Switch - Top Silkscreen
76
Figure 38. Common TX/RX Connector with RF Switch - Bottom
77
Figure 39. Antenna Diversity Reference Design - Schematic
78
Table 29. Antenna Diversity Bill of Materials
79
Figure 40. Antenna Diversity Reference Design - Top
80
Figure 41. Antenna Diversity Reference Design - Top Silkscreen
80
Figure 42. Antenna Diversity Reference Design - Bottom
81
Measurement Results
82
Figure 43. Sensitivity Vs. Data Rate
82
Figure 44. Receiver Selectivity
83
Figure 45. TX Output Power Vs. VDD Voltage
84
Figure 46. TX Output Power Vs Temperature
84
Figure 47. TX Modulation (40 Kbps, 20 Khz Deviation)
85
Figure 48. TX Unmodulated Spectrum (917 Mhz)
85
Figure 49. TX Modulated Spectrum (917 Mhz, 40 Kbps, 20 Khz Deviation, GFSK)
86
Figure 50. Synthesizer Settling Time for 1 Mhz Jump Settled Within 10 Khz
86
Figure 51. Synthesizer Phase Noise (VCOCURR = 11)
87
Application Notes
88
Crystal Selection
88
Layout Practice
88
Matching Network Design
88
Figure 52. RX LNA Matching
88
Table 30. Recommended Crystal Parameters
88
Microcontroller Connection
89
Figure 53. TX Matching and Filtering for Different Bands
89
Figure 54. Microcontroller Connection
89
Table 31. RX Matching for Different Bands
89
Reference Material
90
Complete Register Table and Descriptions
90
Table 32. Register Descriptions
90
Table 33. Interrupt or Status 1 Bit Set/Clear Description
95
Table 34. When Do the Individual Status Bits Get Set/Cleared, if Not Enabled as an Interrupt
96
Table 35. Interrupt or Status 2 Bit Set/Clear Description
98
Table 36. Detailed Description of Status Registers When Not Enabled as Interrupts
99
Table 37. Internal Digital Signals Available on the Digital Test Bus
136
Pin Descriptions: Si4432
161
Ordering Information
162
Package Information
163
Figure 55. Package Dimensions
163
Document Change List
164
Contact Information
166

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