Table of Contents
Advertisement
r identifies registers B, C, D, E, H, L, or A.
Description
The contents of operand m are shifted right 1 bit position. The contents of bit 0 are copied
to the Carry flag, and bit 7 is reset. Bit 0 is the least-significant bit.
Instruction
SRL r
SRL (HL)
SRL (IX+d)
SRL (lY+d)
Condition Bits Affected
S is reset.
Z is set if result is 0; otherwise, it is reset.
H is reset.
P/V is set if parity is even; otherwise, it is reset.
N is reset.
C is data from bit 0 of source register.
Example
Register B contains the following data.
7
6
1
0
Upon the execution of an SRL B instruction, Register B and the Carry flag now contain:
7
6
0
1
UM008011-0816
M Cycles
2
4
6
23 (4, 4, 3, 5, 4, 3)
6
23 (4, 4, 3, 5, 4, 3)
5
4
3
2
1
0
0
1
1
1
5
4
3
2
1
0
0
0
1
1
T States
4 MHz E.T.
8 (4, 4)
15 (4, 4, 4, 3)
0
1
0
C
1
1
Z80 CPU
User Manual
2.00
3.75
5.75
5.75
Z80 Instruction Description
237
Advertisement
Table of Contents
Need help?
Do you have a question about the zilog Z80 and is the answer not in the manual?