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IXYS zilog Z8051 Series Manuals
Manuals and User Guides for IXYS zilog Z8051 Series. We have
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IXYS zilog Z8051 Series manuals available for free PDF download: Manual
IXYS zilog Z8051 Series Manual (313 pages)
8-Bit Microcontrollers
Brand:
IXYS
| Category:
Microcontrollers
| Size: 10 MB
Table of Contents
Table of Contents
4
Overview
13
Description
13
Features
14
Ordering Information
15
Table 1-1 Ordering Information of Z51F3220
15
Development Tools
16
Figure 1.4 Standalone Gang8 (for Mass Production)
18
Block Diagram
19
Figure 2.1 Block Diagram
19
Pin Assignment
20
Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment
20
Figure 3.2 Z51F3220 32SOP Pin Assignment
21
Package Diagram
22
Figure 4.1 44-Pin MQFP Package
22
Figure 4.2 32-Pin SOP Package
23
Pin Description
24
Table 5-1 Normal Pin Description
24
Port Structures
29
General Purpose I/O Port
29
Figure 6.1 General Purpose I/O Port
29
External Interrupt I/O Port
30
Figure 6.2 External Interrupt I/O Port
30
Electrical Characteristics
31
Absolute Maximum Ratings
31
Recommended Operating Conditions
31
Table 7-1 Absolute Maximum Ratings
31
Table 7-2 Recommended Operating Conditions
31
A/D Converter Characteristics
32
Power-On Reset Characteristics
32
Table 7-3 A/D Converter Characteristics
32
Table 7-4 Power-On Reset Characteristics
32
Low Voltage Reset and Low Voltage Indicator Characteristics
33
Table 7-5 LVR and LVI Characteristics
33
High Internal RC Oscillator Characteristics
34
Internal Watch-Dog Timer RC Oscillator Characteristics
34
Table 7-6 High Internal RC Oscillator Characteristics
34
Table 7-7 Internal WDTRC Oscillator Characteristics
34
LCD Voltage Characteristics
35
Table 7-8 LCD Voltage Characteristics
35
DC Characteristics
36
Table 7-9 DC Characteristics
36
AC Characteristics
38
Figure 7.1 AC Timing
38
Table 7-10 AC Characteristics
38
SPI0/1/2 Characteristics
39
Figure 7.2 SPI0/1/2 Timing
39
Table 7-11 SPI0/1/2 Characteristics
39
UART0/1 Characteristics
40
Figure 7.3 Waveform for UART0/1 Timing Characteristics
40
Figure 7.4 Timing Waveform for the UART0/1 Module
40
Table 7-12 UART0/1 Characteristics
40
I2C0/1 Characteristics
41
Figure 7.5 I2C0/1 Timing
41
Table 7-13 I2C0/1 Characteristics
41
Data Retention Voltage in Stop Mode
42
Figure 7.6 Stop Mode Release Timing When Initiated by an Interrupt
42
Figure 7.7 Stop Mode Release Timing When Initiated by RESETB
42
Table 7-14 Data Retention Voltage in Stop Mode
42
Internal Flash Rom Characteristics
43
Input/Output Capacitance
43
Table 7-15 Internal Flash Rom Characteristics
43
Table 7-16 Input/Output Capacitance
43
Main Clock Oscillator Characteristics
44
Figure 7.8 Crystal/Ceramic Oscillator
44
Figure 7.9 External Clock
44
Figure 7.11 External Clock
44
Table 7-17 Main Clock Oscillator Characteristics
44
Sub Clock Oscillator Characteristics
45
Figure 7.10 Crystal Oscillator
45
Table 7-18 Sub Clock Oscillator Characteristics
45
Main Oscillation Stabilization Characteristics
46
Sub Oscillation Characteristics
46
Figure 7.12 Clock Timing Measurement at XIN
46
Figure 7.13 Clock Timing Measurement at SXIN
46
Table 7-19 Main Oscillation Stabilization Characteristics
46
Table 7-20 Sub Oscillation Stabilization Characteristics
46
Operating Voltage Range
47
Figure 7.14 Operating Voltage Range
47
Recommended Circuit and Layout
48
Figure 7.15 Recommended Circuit and Layout
48
Typical Characteristics
49
Figure 7.16 RUN (IDD1 ) Current
49
Figure 7.17 IDLE (IDD2) Current
49
Figure 7.18 SUB RUN (IDD3) Current
50
Figure 7.19 SUB IDLE (IDD4) Current
50
Figure 7.20 STOP (IDD5) Current
51
Memory
52
Program Memory
52
Figure 8.1 Program Memory
53
Data Memory
54
Figure 8.2 Data Memory Map
54
Figure 8.3 Lower 128 Bytes RAM
55
XRAM Memory
56
Figure 8.4 XDATA Memory Area
56
SFR Map
57
Table 8-1 SFR Map Summary
57
Table 8-2 SFR Map Summary
58
Table 8-3 SFR Map
59
I/O Ports
66
Port Register
66
Table 9-1 Port Register Map
67
P0 Port
68
P1 Port
70
P2 Port
72
P3 Port
73
P4 Port
74
P5 Port
75
Port Function
76
Interrupt Controller
85
Overview
85
Table 10-1 Interrupt Group Priority Level
85
External Interrupt
86
Figure 10.1 External Interrupt Description
86
Block Diagram
87
Figure 10.2 Block Diagram of Interrupt
87
Interrupt Vector Table
88
Interrupt Sequence
88
Table 10-2 Interrupt Vector Address Table
88
Figure 10.3 Interrupt Vector Address Table
89
Effective Timing after Controlling Interrupt Bit
90
Figure 10.4 Effective Timing of Interrupt Enable Register
90
Figure 10.5 Effective Timing of Interrupt Flag Register
90
Multi Interrupt
91
Figure 10.6 Effective Timing of Interrupt
91
Interrupt Enable Accept Timing
92
Interrupt Service Routine Address
92
Saving/Restore General-Purpose Registers
92
Figure 10.7 Interrupt Response Timing Diagram
92
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP
92
Figure 10.9 Saving/Restore Process Diagram and Sample Source
92
Interrupt Timing
93
Interrupt Register Overview
93
Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
93
Interrupt Register Description
95
Table 10-3 Interrupt Register Map
95
Peripheral Hardware
102
Clock Generator
102
Figure 11.1 Clock Generator Block Diagram
102
Table 11-1 Clock Generator Register Map
103
Basic Interval Timer
105
Figure 11.2 Basic Interval Timer Block Diagram
105
Table 11-2 Basic Interval Timer Register Map
106
Watch Dog Timer
108
Figure 11.3 Watch Dog Timer Interrupt Timing Waveform
108
Figure 11.4 Watch Dog Timer Block Diagram
109
Table 11-3 Watch Dog Timer Register Map
109
Watch Timer
111
Figure 11.5 Watch Timer Block Diagram
111
Table 11-4 Watch Timer Register Map
112
Timer 0
114
Table 11-5 Timer 0 Operating Modes
114
Figure 11.6 8-Bit Timer/Counter Mode for Timer 0
115
Figure 11.7 8-Bit Timer/Counter 0 Example
115
Figure 11.8 8-Bit PWM Mode for Timer 0
116
Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0
117
Figure 11.10 8-Bit Capture Mode for Timer 0
118
Figure 11.11 Input Capture Mode Operation for Timer 0
119
Figure 11.12 Express Timer Overflow in Capture Mode
119
Figure 11.13 8-Bit Timer 0 Block Diagram
120
Table 11-6 Timer 0 Register Map
121
Timer 1
123
Table 11-7 Timer 1 Operating Modes
123
Figure 11.14 16-Bit Timer/Counter Mode for Timer 1
124
Figure 11.15 16-Bit Timer/Counter 1 Example
124
Figure 11.16 16-Bit Capture Mode for Timer 1
125
Figure 11.17 Input Capture Mode Operation for Timer 1
126
Figure 11.18 Express Timer Overflow in Capture Mode
126
Figure 11.19 16-Bit PPG Mode for Timer 1
127
Figure 11.20 16-Bit PPG Mode Timming Chart for Timer 1
128
Figure 11.21 16-Bit Timer/Counter Mode for Timer 1 and Block Diagram
129
Table 11-8 Timer 2 Register Map
129
Timer 2
133
Table 11-9 Timer 2 Operating Modes
133
Figure 11.22 16-Bit Timer/Counter Mode for Timer 2
134
Figure 11.23 16-Bit Timer/Counter 2 Example
135
Figure 11.24 16-Bit Capture Mode for Timer 2
136
Figure 11.25 Input Capture Mode Operation for Timer 2
137
Figure 11.26 Express Timer Overflow in Capture Mode
137
Figure 11.27 16-Bit PPG Mode for Timer 2
138
Figure 11.28 16-Bit PPG Mode Timming Chart for Timer 2
139
Figure 11.29 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram
140
Table 11-10 Timer 3 Register Map
140
Timer 3, 4
144
Table 11-11 Timer 3, 4 Operating Modes
144
Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4
145
Figure 11.31 16-Bit Timer/Counter Mode for Timer 3
146
Figure 11.32 8-Bit Capture Mode for Timer 3, 4
148
Figure 11.33 16-Bit Capture Mode for Timer 3
149
Table 11-12 PWM Frequency Vs. Resolution at 8 Mhz
150
Table 11-13 PWM Channel Polarity
150
Figure 11.34 10-Bit PWM Mode (Force 6-Ch)
151
Figure 11.35 10-Bit PWM Mode (Force All-Ch)
152
Figure 11.36 Example of PWM at 4 Mhz
153
Figure 11.37 Example of Changing the Period in Absolute Duty Cycle at 4 Mhz
153
Figure 11.38 Example of PWM Output Waveform
154
Figure 11.39 Example of PWM Waveform in Back-To-Back Mode at 4 Mhz
154
Figure 11.40 Example of Phase Correction and Frequency Correction of PWM
155
Figure 11.41 Example of PWM External Synchronization with BLNK Input
155
Figure 11.42 Example of Force Drive All Channel with A-Ch
156
Figure 11.43 Example of Force Drive 6-Ch Mode
157
Figure 11.44 Example of PWM Delay
160
Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram
160
Figure 11.46 16-Bit Timer 3 Block Diagram
161
Figure 11.47 10-Bit PWM Timer 4 Block Diagram
161
Table 11-14 Timer 3, 4 Register Map
162
Buzzer Driver
173
Figure 11.48 Buzzer Driver Block Diagram
173
Table 11-15 Buzzer Frequency at 8 Mhz
173
Table 11-16 Buzzer Driver Register Map
174
Spi 2
175
Figure 11.49 SPI 2 Block Diagram
175
Figure 11.50 SPI 2 Transmit/Receive Timing Diagram at CPHA = 0
177
Figure 11.51 SPI 2 Transmit/Receive Timing Diagram at CPHA = 1
177
Table 11-17 SPI 2 Register Map
178
12-Bit A/D Converter
181
Figure 11.52 12-Bit ADC Block Diagram
182
Figure 11.53 A/D Analog Input Pin with Capacitor
182
Figure 11.54 A/D Power (AVREF) Pin with Capacitor
182
Figure 11.55 ADC Operation for Align Bit
183
Figure 11.56 A/D Converter Operation Flow
185
Table 11-18 ADC Register Map
185
Usi0 (Uart + Spi + I2C)
188
Figure 11.57 USI0 UART Block Diagram
190
Figure 11.58 Clock Generation Block Diagram (USI0)
191
Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting
191
Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
192
Figure 11.60 Frame Format (USI0)
193
Figure 11.61 Asynchronous Start Bit Sampling (USI0)
197
Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0)
197
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
198
Table 11-20 CPOL0 Functionality
199
Figure 11.64 USI0 SPI Clock Formats When CPHA0=0
200
Figure 11.65 USI0 SPI Clock Formats When CPHA0=1
201
Figure 11.66 USI0 SPI Block Diagram
202
Figure 11.67 Bit Transfer on the I2C-Bus (USI0)
203
Figure 11.68 START and STOP Condition (USI0)
204
Figure 11.69 Data Transfer on the I2C-Bus (USI0)
204
Figure 11.70 Acknowledge on the I2C-Bus (USI0)
205
Figure 11.71 Clock Synchronization During Arbitration Procedure (USI0)
206
Figure 11.72 Arbitration Procedure of Two Masters (USI0)
206
Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)
208
Figure 11.74 Formats and States in the Master Receiver Mode (USI0)
210
Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)
212
Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)
214
Figure 11.77 USI0 I2C Block Diagram
215
Table 11-21 USI0 Register Map
216
Usi1 (Uart + Spi + I2C)
225
Figure 11.78 USI1 UART Block Diagram
227
Figure 11.79 Clock Generation Block Diagram (USI1)
228
Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting
228
Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
229
Figure 11.81 Frame Format (USI1)
230
Figure 11.82 Asynchronous Start Bit Sampling (USI1)
234
Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1)
234
Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)
235
Table 11-23 CPOL1 Functionality
236
Figure 11.85 USI1 SPI Clock Formats When CPHA1=0
237
Figure 11.86 USI1 SPI Clock Formats When CPHA1=1
238
Figure 11.87 USI1 SPI Block Diagram
239
Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
240
Figure 11.89 START and STOP Condition (USI1)
241
Figure 11.90 Data Transfer on the I2C-Bus (USI1)
241
Figure 11.91 Acknowledge on the I2C-Bus (USI1)
242
Figure 11.92 Clock Synchronization During Arbitration Procedure (USI1)
243
Figure 11.93 Arbitration Procedure of Two Masters (USI1)
243
Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)
245
Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
247
Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)
249
Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)
251
Figure 11.98 USI1 I2C Block Diagram
252
Table 11-24 USI1 Register Map
253
Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies
262
LCD Driver
263
Figure 11.99 LCD Circuit Block Diagram
264
Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)
265
Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)
266
Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)
267
Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)
268
Figure 11.104 Internal Resistor Bias Connection
269
Figure 11.105 External Resistor Bias Connection
270
Figure 11.106 LCD Circuit Block Diagram
271
Table 11-26 LCD Register Map
271
Power down Operation
275
Overview
275
Peripheral Operation in IDLE/STOP Mode
275
Table 12-1 Peripheral Operation During Power down Mode
275
IDLE Mode
276
Figure 12.1 IDLE Mode Release Timing by External Interrupt
276
STOP Mode
277
Figure 12.2 STOP Mode Release Timing by External Interrupt
277
Release Operation of STOP Mode
278
Figure 12.3 STOP Mode Release Flow
278
Table 12-2 Power down Operation Register Map
279
Reset
280
Overview
280
Reset Source
280
RESET Block Diagram
280
Figure 13.1 RESET Block Diagram
280
Table 13-1 Reset State
280
RESET Noise Canceller
281
Power on RESET
281
Figure 13.2 Reset Noise Canceller Timer Diagram
281
Figure 13.3 Fast VDD Rising Time
281
Figure 13.4 Internal RESET Release Timing on Power-Up
281
Figure 13.5 Configuration Timing When Power-On
282
Figure 13.6 Boot Process Waveform
282
Table 13-2 Boot Process Description
283
External RESETB Input
284
Figure 13.7 Timing Diagram after RESET
284
Figure 13.8 Oscillator Generating Waveform Example
284
Brown out Detector Processor
285
Figure 13.9 Block Diagram of BOD
285
Figure 13.10 Internal Reset at the Power Fail Situation
285
LVI Block Diagram
286
Figure 13.11 Configuration Timing When BOD RESET
286
Figure 13.12 LVI Diagram
286
Table 13-3 Reset Operation Register Map
287
On-Chip Debug System
290
Overview
290
Two-Pin External Interface
291
Figure 14.1 Block Diagram of On-Chip Debug System
291
Figure 14.2 10-Bit Transmission Packet
291
Figure 14.3 Data Transfer on the Twin Bus
292
Figure 14.4 Bit Transfer on the Serial Bus
292
Figure 14.5 Start and Stop Condition
293
Figure 14.6 Acknowledge on the Serial Bus
293
Figure 14.7 Clock Synchronization During Wait Procedure
294
Figure 14.8 Connection of Transmission
295
Flash Memory
296
Overview
296
Figure 15.1 Flash Program ROM Structure
297
Table 15-1Flash Memory Register Map
298
Configure Option
307
Configure Option Control
307
Appendix
308
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IXYS zilog Z8051 Series Manual (312 pages)
8-Bit Microcontrollers
Brand:
IXYS
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
4
1 Overview
13
Description
13
Features
14
Ordering Information
15
Table 1-1 Ordering Information of Z51F3220
15
Development Tools
16
2 Block Diagram
19
Figure 2.1 Block Diagram
19
3 Pin Assignment
20
Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment
20
Figure 3.2 Z51F3220 32SOP Pin Assignment
21
4 Package Diagram
22
Figure 4.1 44-Pin MQFP Package
22
Figure 4.2 32-Pin SOP Package
23
5 Pin Description
24
Table 5-1 Normal Pin Description
24
6 Port Structures
29
General Purpose I/O Port
29
Figure 6.1 General Purpose I/O Port
29
External Interrupt I/O Port
30
Figure 6.2 External Interrupt I/O Port
30
7 Electrical Characteristics
31
Absolute Maximum Ratings
31
Recommended Operating Conditions
31
Table 7-1 Absolute Maximum Ratings
31
Table 7-2 Recommended Operating Conditions
31
A/D Converter Characteristics
32
Power-On Reset Characteristics
32
Table 7-3 A/D Converter Characteristics
32
Table 7-4 Power-On Reset Characteristics
32
Low Voltage Reset and Low Voltage Indicator Characteristics
33
Table 7-5 LVR and LVI Characteristics
33
High Internal RC Oscillator Characteristics
34
Internal Watch-Dog Timer RC Oscillator Characteristics
34
Table 7-6 High Internal RC Oscillator Characteristics
34
Table 7-7 Internal WDTRC Oscillator Characteristics
34
LCD Voltage Characteristics
35
Table 7-8 LCD Voltage Characteristics
35
DC Characteristics
36
Table 7-9 DC Characteristics
36
AC Characteristics
38
Figure 7.1 AC Timing
38
Table 7-10 AC Characteristics
38
SPI0/1/2 Characteristics
39
Figure 7.2 SPI0/1/2 Timing
39
Table 7-11 SPI0/1/2 Characteristics
39
UART0/1 Characteristics
40
Figure 7.3 Waveform for UART0/1 Timing Characteristics
40
Figure 7.4 Timing Waveform for the UART0/1 Module
40
Table 7-12 UART0/1 Characteristics
40
I2C0/1 Characteristics
41
Figure 7.5 I2C0/1 Timing
41
Table 7-13 I2C0/1 Characteristics
41
Data Retention Voltage in Stop Mode
42
Figure 7.6 Stop Mode Release Timing When Initiated by an Interrupt
42
Figure 7.7 Stop Mode Release Timing When Initiated by RESETB
42
Table 7-14 Data Retention Voltage in Stop Mode
42
Internal Flash Rom Characteristics
43
Input/Output Capacitance
43
Table 7-15 Internal Flash Rom Characteristics
43
Table 7-16 Input/Output Capacitance
43
Main Clock Oscillator Characteristics
44
Figure 7.8 Crystal/Ceramic Oscillator
44
Figure 7.9 External Clock
44
Figure 7.11 External Clock
44
Table 7-17 Main Clock Oscillator Characteristics
44
Sub Clock Oscillator Characteristics
45
Figure 7.10 Crystal Oscillator
45
Table 7-18 Sub Clock Oscillator Characteristics
45
Main Oscillation Stabilization Characteristics
46
Sub Oscillation Characteristics
46
Figure 7.12 Clock Timing Measurement at XIN
46
Figure 7.13 Clock Timing Measurement at SXIN
46
Table 7-19 Main Oscillation Stabilization Characteristics
46
Table 7-20 Sub Oscillation Stabilization Characteristics
46
Operating Voltage Range
47
Figure 7.14 Operating Voltage Range
47
Recommended Circuit and Layout
48
Figure 7.15 Recommended Circuit and Layout
48
Typical Characteristics
49
Figure 7.16 RUN (IDD1 ) Current
49
Figure 7.17 IDLE (IDD2) Current
49
Figure 7.18 SUB RUN (IDD3) Current
50
Figure 7.19 SUB IDLE (IDD4) Current
50
Figure 7.20 STOP (IDD5) Current
51
8 Memory
52
Program Memory
52
Figure 8.1 Program Memory
53
Data Memory
54
Figure 8.2 Data Memory Map
54
Figure 8.3 Lower 128 Bytes RAM
55
XRAM Memory
56
Figure 8.4 XDATA Memory Area
56
SFR Map
57
Table 8-1 SFR Map Summary
57
Table 8-2 SFR Map Summary
58
Table 8-3 SFR Map
59
9 I/O Ports
66
Port Register
66
Table 9-1 Port Register Map
67
P0 Port
68
P1 Port
70
P2 Port
72
P3 Port
73
P4 Port
74
P5 Port
75
Port Function
76
10 Interrupt Controller
85
Overview
85
Table 10-1 Interrupt Group Priority Level
85
External Interrupt
86
Figure 10.1 External Interrupt Description
86
Block Diagram
87
Figure 10.2 Block Diagram of Interrupt
87
Interrupt Vector Table
88
Interrupt Sequence
88
Table 10-2 Interrupt Vector Address Table
88
Figure 10.3 Interrupt Vector Address Table
89
Effective Timing after Controlling Interrupt Bit
90
Figure 10.4 Effective Timing of Interrupt Enable Register
90
Figure 10.5 Effective Timing of Interrupt Flag Register
90
Multi Interrupt
91
Figure 10.6 Effective Timing of Interrupt
91
Interrupt Enable Accept Timing
92
Interrupt Service Routine Address
92
Saving/Restore General-Purpose Registers
92
Figure 10.7 Interrupt Response Timing Diagram
92
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP
92
Figure 10.9 Saving/Restore Process Diagram and Sample Source
92
Interrupt Timing
93
Interrupt Register Overview
93
Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
93
Interrupt Register Description
95
Table 10-3 Interrupt Register Map
95
11 Peripheral Hardware
102
Clock Generator
102
Figure 11.1 Clock Generator Block Diagram
102
Table 11-1 Clock Generator Register Map
103
Basic Interval Timer
105
Figure 11.2 Basic Interval Timer Block Diagram
105
Table 11-2 Basic Interval Timer Register Map
106
Watch Dog Timer
108
Figure 11.3 Watch Dog Timer Interrupt Timing Waveform
108
Figure 11.4 Watch Dog Timer Block Diagram
109
Table 11-3 Watch Dog Timer Register Map
109
Watch Timer
111
Figure 11.5 Watch Timer Block Diagram
111
Table 11-4 Watch Timer Register Map
112
Timer 0
114
Table 11-5 Timer 0 Operating Modes
114
Figure 11.7 8-Bit Timer/Counter 0 Example
115
Figure 11.12 Express Timer Overflow in Capture Mode
119
Figure 11.13 8-Bit Timer 0 Block Diagram
120
Table 11-6 Timer 0 Register Map
121
Timer 1
123
Table 11-7 Timer 1 Operating Modes
123
Figure 11.15 16-Bit Timer/Counter 1 Example
124
Figure 11.18 Express Timer Overflow in Capture Mode
126
Figure 11.21 16-Bit Timer/Counter Mode for Timer 1 and Block Diagram
129
Table 11-8 Timer 2 Register Map
129
Timer 2
133
Table 11-9 Timer 2 Operating Modes
133
Figure 11.23 16-Bit Timer/Counter 2 Example
135
Figure 11.26 Express Timer Overflow in Capture Mode
137
Figure 11.29 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram
140
Table 11-10 Timer 3 Register Map
140
Timer 3, 4
144
Table 11-11 Timer 3, 4 Operating Modes
144
Table 11-12 PWM Frequency Vs. Resolution at 8 Mhz
150
Table 11-13 PWM Channel Polarity
150
Figure 11.34 10-Bit PWM Mode (Force 6-Ch)
151
Figure 11.35 10-Bit PWM Mode (Force All-Ch)
152
Figure 11.36 Example of PWM at 4 Mhz
153
Figure 11.37 Example of Changing the Period in Absolute Duty Cycle at 4 Mhz
153
Figure 11.38 Example of PWM Output Waveform
154
Figure 11.39 Example of PWM Waveform in Back-To-Back Mode at 4 Mhz
154
Figure 11.40 Example of Phase Correction and Frequency Correction of PWM
155
Figure 11.41 Example of PWM External Synchronization with BLNK Input
155
Figure 11.42 Example of Force Drive All Channel with A-Ch
156
Figure 11.43 Example of Force Drive 6-Ch Mode
157
Figure 11.44 Example of PWM Delay
160
Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram
160
Figure 11.46 16-Bit Timer 3 Block Diagram
161
Figure 11.47 10-Bit PWM Timer 4 Block Diagram
161
Table 11-14 Timer 3, 4 Register Map
162
Buzzer Driver
173
Figure 11.48 Buzzer Driver Block Diagram
173
Table 11-15 Buzzer Frequency at 8 Mhz
173
Table 11-16 Buzzer Driver Register Map
174
Spi 2
175
Figure 11.49 SPI 2 Block Diagram
175
Table 11-17 SPI 2 Register Map
178
12-Bit A/D Converter
181
Figure 11.52 12-Bit ADC Block Diagram
182
Figure 11.53 A/D Analog Input Pin with Capacitor
182
Figure 11.54 A/D Power (AVREF) Pin with Capacitor
182
Figure 11.55 ADC Operation for Align Bit
183
Figure 11.56 A/D Converter Operation Flow
184
Table 11-18 ADC Register Map
184
Usi0 (Uart + Spi + I2C)
187
Figure 11.57 USI0 UART Block Diagram
189
Figure 11.58 Clock Generation Block Diagram (USI0)
190
Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting
190
Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
191
Figure 11.60 Frame Format (USI0)
192
Figure 11.61 Asynchronous Start Bit Sampling (USI0)
196
Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0)
196
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
197
Table 11-20 CPOL0 Functionality
198
Figure 11.64 USI0 SPI Clock Formats When CPHA0=0
199
Figure 11.65 USI0 SPI Clock Formats When CPHA0=1
200
Figure 11.66 USI0 SPI Block Diagram
201
Figure 11.67 Bit Transfer on the I2C-Bus (USI0)
202
Figure 11.68 START and STOP Condition (USI0)
203
Figure 11.69 Data Transfer on the I2C-Bus (USI0)
203
Figure 11.70 Acknowledge on the I2C-Bus (USI0)
204
Figure 11.71 Clock Synchronization During Arbitration Procedure (USI0)
205
Figure 11.72 Arbitration Procedure of Two Masters (USI0)
205
Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)
207
Figure 11.74 Formats and States in the Master Receiver Mode (USI0)
209
Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)
211
Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)
213
Figure 11.77 USI0 I2C Block Diagram
214
Table 11-21 USI0 Register Map
215
Usi1 (Uart + Spi + I2C)
224
Figure 11.78 USI1 UART Block Diagram
226
Figure 11.79 Clock Generation Block Diagram (USI1)
227
Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting
227
Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
228
Figure 11.81 Frame Format (USI1)
229
Figure 11.82 Asynchronous Start Bit Sampling (USI1)
233
Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1)
233
Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)
234
Table 11-23 CPOL1 Functionality
235
Figure 11.85 USI1 SPI Clock Formats When CPHA1=0
236
Figure 11.86 USI1 SPI Clock Formats When CPHA1=1
237
Figure 11.87 USI1 SPI Block Diagram
238
Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
239
Figure 11.89 START and STOP Condition (USI1)
240
Figure 11.90 Data Transfer on the I2C-Bus (USI1)
240
Figure 11.91 Acknowledge on the I2C-Bus (USI1)
241
Figure 11.92 Clock Synchronization During Arbitration Procedure (USI1)
242
Figure 11.93 Arbitration Procedure of Two Masters (USI1)
242
Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)
244
Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
246
Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)
248
Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)
250
Figure 11.98 USI1 I2C Block Diagram
251
Table 11-24 USI1 Register Map
252
Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies
261
LCD Driver
262
Figure 11.99 LCD Circuit Block Diagram
263
Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)
264
Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)
265
Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)
266
Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)
267
Figure 11.104 Internal Resistor Bias Connection
268
Figure 11.105 External Resistor Bias Connection
269
Figure 11.106 LCD Circuit Block Diagram
270
Table 11-26 LCD Register Map
270
12 Power down Operation
274
Overview
274
Peripheral Operation in IDLE/STOP Mode
274
Table 12-1 Peripheral Operation During Power down Mode
274
IDLE Mode
275
Figure 12.1 IDLE Mode Release Timing by External Interrupt
275
STOP Mode
276
Figure 12.2 STOP Mode Release Timing by External Interrupt
276
Release Operation of STOP Mode
277
Figure 12.3 STOP Mode Release Flow
277
Table 12-2 Power down Operation Register Map
278
13 Reset
279
Overview
279
Reset Source
279
RESET Block Diagram
279
Figure 13.1 RESET Block Diagram
279
Table 13-1 Reset State
279
RESET Noise Canceller
280
Power on RESET
280
Figure 13.2 Reset Noise Canceller Timer Diagram
280
Figure 13.3 Fast VDD Rising Time
280
Figure 13.4 Internal RESET Release Timing on Power-Up
280
Figure 13.5 Configuration Timing When Power-On
281
Figure 13.6 Boot Process Waveform
281
Table 13-2 Boot Process Description
282
External RESETB Input
283
Figure 13.7 Timing Diagram after RESET
283
Figure 13.8 Oscillator Generating Waveform Example
283
Brown out Detector Processor
284
Figure 13.9 Block Diagram of BOD
284
Figure 13.10 Internal Reset at the Power Fail Situation
284
LVI Block Diagram
285
Figure 13.11 Configuration Timing When BOD RESET
285
Figure 13.12 LVI Diagram
285
Table 13-3 Reset Operation Register Map
286
14 On-Chip Debug System
289
Overview
289
Two-Pin External Interface
290
Figure 14.1 Block Diagram of On-Chip Debug System
290
Figure 14.2 10-Bit Transmission Packet
290
Figure 14.3 Data Transfer on the Twin Bus
291
Figure 14.4 Bit Transfer on the Serial Bus
291
Figure 14.5 Start and Stop Condition
292
Figure 14.6 Acknowledge on the Serial Bus
292
Figure 14.7 Clock Synchronization During Wait Procedure
293
Figure 14.8 Connection of Transmission
294
15 Flash Memory
295
Overview
295
Figure 15.1 Flash Program ROM Structure
296
Table 15-1Flash Memory Register Map
297
16 Configure Option
306
Configure Option Control
306
17 Appendix
307
IXYS zilog Z8051 Series Manual (189 pages)
Brand:
IXYS
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
4
Overview
11
Description
11
Features
11
Ordering Information
12
Table 1-1 Ordering Information for the Z51F6412 MCU
12
Development Tools
13
Figure 1-2 Single Programmer
15
Figure 1-3 Gang Programmer
15
Block Diagram
16
Figure 2-1 Z51F6412 Block Diagram
16
Pin Assignmnet
17
Figure 3-1 Z51GF64 80-Pin LQFP Assignment
17
Figure 3-2 Z51GF64A 64 Pin LQFP Assignment
18
Package Diagram
19
Figure 4-1 80 Pin LQFP Package
19
Figure 4-2 64 Pin LQFP Package
20
Pin Description
21
Table 5-1 Normal Pin Description
21
Port Structures
24
General Purpose I/O Port
24
Figure 6-1 General Purpose I/O Port
24
External Interrupt I/O Port
25
Figure 6-2 External Interrupt I/O Port
25
Electrical Characteristics
26
Absolute Maximum Ratings
26
Recommended Operating Conditions
26
Table 7-1 Absolute Maximum Ratings
26
Table 7-2 Recommended Operation Conditions
26
A/D Converter Characteristics
27
Voltage Dropout Converter Characteristics
27
Table 7-3 A/D Converter Characteristics
27
Table 7-4 Voltage Dropout Converter Characteristics
27
Power-On Reset Characteristics
28
Brown out Detector Characteristics
28
Internal RC Oscillator Characteristics
28
Table 7-5 Power-On Reset Characteristics
28
Table 7-6 Brown out Detector Characteristics
28
Table 7-7 Internal RC Oscillator Characteristics
28
Ring-Oscillator Characteristics
29
PLL Characteristics
29
Table 7-8 Ring-Oscillator Characteristics
29
Table 7-9 PLL Characteristics
29
DC Characteristics
30
Table 7-10 DC Characteristics
30
AC Characteristics
31
Figure 7-1 AC Timing
31
Table 7-11 AC Characteristics
31
SPI Characteristics
32
Figure 7-2 SPI Timing
32
Table 7-12 SPI Characteristics
32
Typical Characteristics
33
Memory
34
Program Memory
34
Figure 8-1 Program Memory
34
Data Memory
35
Figure 8-2 Data Memory Map
35
XSRAM Memory
36
Figure 8-3 Lower 128 Bytes RAM
36
Figure 8-4 XDATA Memory Area
36
SFR Map
37
Table 8-1 SFR Map Summary
37
I/O Ports
40
Port Register
40
Table 9-1 Register Map
41
Px Port
42
Interrupt Controller
45
Overview
45
Table 10-1 Interrupt Group Priority Level
45
External Interrupt
46
Figure 10-1 External Interrupt Description
46
Block Diagram
47
Figure 10-2 Block Diagram of Interrupt
47
Interrupt Vector Table
48
Table 10-2 Interrupt Vector Address Table
48
Interrupt Sequence
49
Figure 10-3 Interrupt Vector Address Table
49
Effective Timing after Controlling Interrupt Bit
50
Figure 10-4 Effective Time of Interrupt Request after Setting Iex Registers
50
Multi Interrupt
51
Figure 10-5 Execution of Multi Interrupt
51
Interrupt Enable Accept Timing
52
Interrupt Service Routine Address
52
Saving/Restore General-Purpose Registers
52
Figure 10-6 Interrupt Response Timing Diagram
52
Figure 10-7 Correspondence between Vector Table Address and the Entry Address of ISP
52
Figure 10-8 Saving/Restore Process Diagram & Sample Source
52
Interrupt Timing
53
Figure 10-9 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
53
Interrupt Register Overview
54
Interrupt Register Description
55
Table 10-3 Register Map
55
Peripheral Hardware
61
Clock Generator
61
Figure 11-1 Clock Generator Block Diagram
61
Table 11-1 Register Map
62
Table 11-2 VDC Current Consumption
64
Bit
65
Figure 11-2 BIT Block Diagram
65
Table 11-3 Register Map
65
Wdt
67
Figure 11-3 WDT Block Diagram
67
Table 11-4 Register Map
67
Figure 11-4 WDT Interrupt Timing Waveform
69
Figure 11-5 Watch Timer Block Diagram
70
Table 11-5 Register Map
70
Timer/Pwm
73
Table 11-6 Operating Modes of Timer
73
Figure 11-6 Bit Timer/Event Counter2, 3 Block Diagram
74
Figure 11-7 Timer/Event Counter0, 1 Example
75
Figure 11-8 Operation Example of Timer/Event Counter0, 1
75
Figure 11-9 16 Bit Timer/Event Counter0, 1 Block Diagram
76
Figure 11-10 8-Bit Capture Mode for Timer0, 1
77
Figure 11-11 Input Capture Mode Operation of Timer 0, 1
78
Figure 11-12 Express Timer Overflow in Capture Mode
78
Figure 11-13 16-Bit Capture Mode of Timer 0, 1
79
Figure 11-14 PWM Mode
80
Table 11-7 PWM Frequency Vs. Resolution at 8 Mhz
80
Figure 11-15 Example of PWM at 4Mhz
81
Figure 11-16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz
81
Table 11-8 Register Map
82
Figure 11-17 Timer4 16-Bit Mode Block Diagram
86
Figure 11-18 16-Bit Capture Mode of Timer X
87
Figure 11-19 PWM Mode
88
Table 11-9 PWM Frequency Vs. Resolution at 8 Mhz
88
Figure 11-20 Example of PWM at 8Mhz
89
Table 11-10 Register Map
89
Buzzer Driver
95
Figure 11-21 Buzzer Driver Block Diagram
95
Table 11-11 Buzzer Frequency at 16Mhz
95
Table 11-12 Register Map
96
Usart
97
Figure 11-22 USART Block Diagram
98
Figure 11-23 Clock Generation Block Diagram
99
Table 11-13 Equations for Calculating Baud Rate Register Setting
99
Figure 11-24 Synchronous Mode Xckn Timing
100
Figure 11-25 Frame Format
101
Figure 11-26 Start Bit Sampling
105
Figure 11-27 Sampling of Data and Parity Bit
105
Figure 11-28 Stop Bit Sampling and Next Start Bit Sampling
106
Table 11-14 CPOL Funtionality
106
Figure 11-29 SPI Clock Formats When UCPHA=0
107
Figure 11-30 SPI Clock Formats When UCPHA=1
108
Table 11-15 Register Map
108
Table 11-16 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
114
Spi
115
Figure 11-31 SPI Block Diagram
115
Figure 11-32 SPI Transmit/Receive Timing Diagram at CPHA = 0
117
Figure 11-33 SPI Transmit/Receive Timing Diagram at CPHA = 1
117
Table 11-17 Register Map
117
Table 15-1 Register Map
117
I 2 C
120
Figure 11-34 I 2 C Block Diagram
120
Figure 11-35 Bit Transfer on the I C-Bus
121
Figure 11-36 START and STOP Condition
121
Figure 11-37 Data Transfer on the I 2 C-Bus
122
Figure 11-38 Acknowledge on the I 2 C-Bus
122
Figure 11-39 Clock Synchronization During Arbitration Procedure
123
Figure 11-40 Arbitration Procedure of Two Masters
123
Figure 11-41 Formats and States in the Master Transmitter Mode
126
Figure 11-42 Formats and States in the Master Receiver Mode
128
Figure 11-43 Formats and States in the Slave Transmitter Mode
130
Figure 11-44 Formats and States in the Slave Receiver Mode
132
12-Bit A/D Converter
137
Figure 11-45 ADC Block Diagram
137
Figure 11-46 A/D Analog Input Pin Connecting Capacitor
138
Figure 11-47 A/D Power(AVDD) Pin Connecting Capacitor
138
Figure 11-48 ADC Operation for Align Bit
138
Figure 11-49 Converter Operation Flow
139
Calculator_Ai
143
Figure 11-50 Calculator Block Diagram
143
Power down Operation
148
Overview
148
Peripheral Operation in IDLE/STOP Mode
148
Table 12-1 Peripheral Operation During Power down Mode
148
IDLE Mode
149
Figure 12-1 IDLE Mode Release Timing by External Interrupt
149
Figure 12-2 IDLE Mode Release Timing by /RESET
149
STOP Mode
150
Figure 12-3 STOP Mode Release Timing by External Interrupt
150
Figure 12-4 Mode Release Timing by /RESET
150
Release Operation of STOP1, 2 Mode
151
Figure 12-5 STOP1, 2 Mode Release Flow
151
Table 12-2 Register Map
152
Reset
153
Overview
153
Reset Source
153
Block Diagram
153
Figure 13-1 RESET Block Diagram
153
Table 13-1 Reset State
153
RESET Noise Canceller
154
Power on RESET
154
Figure 13-2 Reset Noise Canceller Time Diagram
154
Figure 13-3 Fast VDD Rising Time
154
Figure 13-4 Internal RESET Release Timing on Power-Up
155
Figure 13-5 Configuration Timing When Power-On
155
Figure 13-6 Boot Process Waveform
156
Table 13-2 Boot Process Description
156
External RESETB Input
157
Figure 13-7 Timing Diagram after RESET
157
Figure 13-8 Oscillator Generating Waveform Example
157
Brown out Detector Processor
158
Figure 13-9 Block Diagram of BOD
158
Figure 13-10 Internal Reset at the Power Fail Situation
158
Figure 13-11 Configuration Timing When BOD RESET
159
Table 13-3 Register Map
159
On-Chip Debug System
161
Overview
161
Two-Pin External Interface
162
Figure 14-1 Block Diagram of On-Chip Debug System
162
Figure 14-2 10-Bit Transmission Packet
163
Figure 14-3 Data Transfer on the Twin Bus
163
Figure 14-4 Bit Transfer on the Serial Bus
164
Figure 14-5 Start and Stop Condition
164
Figure 14-6 Acknowledge on the Serial Bus
164
Figure 14-7 Clock Synchronization During Wait Procedure
165
Figure 14-8 Connection of Transmission
165
Memory Programming
166
Overview
166
Flash Control and Status Register
166
Table 15-2 Program/Erase Time
168
Memory Map
170
Figure 15-1 Flash Memory Map
170
Figure 15-2 Address Configuration of Flash Memory
171
Serial In-System Program Mode
172
Figure 15-3 the Sequence of Page Program and Erase of Flash Memory
172
Figure 15-4 the Sequence of Bulk Erase of Flash Memory
173
Parallel Mode
177
Figure 15-5 Pin Diagram for Parallel Programming
177
Figure 15-6 Parallel Byte Read Timing of Program Memory
178
Figure 15-7 Parallel Byte Write Timing of Program Memory
179
Mode Entrance Method of ISP and Byte-Parallel Mode
180
Figure 15-8 ISP Mode
180
Figure 15-9 Byte-Parallel Mode
180
Security
181
Configure Option
182
Configure Option Control Register
182
Appendix
183
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