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Z8 Encore! Z8F0230
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Manuals and User Guides for IXYS Z8 Encore! Z8F0230. We have
1
IXYS Z8 Encore! Z8F0230 manual available for free PDF download: Product Specification
IXYS Z8 Encore! Z8F0230 Product Specification (256 pages)
High-Performance 8-Bit Microcontrollers
Brand:
IXYS
| Category:
Microcontrollers
| Size: 16 MB
Table of Contents
Revision History
3
Table of Contents
4
List of Figures
10
Overview
18
Features
18
Part Selection Guide
19
Table 1. Z8 Encore! F0830 Series Family Part Selection Guide
19
Block Diagram
20
Figure 1. Z8 Encore! F0830 Series Block Diagram
20
CPU and Peripheral Overview
21
General Purpose Input/Output
21
Flash Controller
21
Nonvolatile Data Storage
22
Internal Precision Oscillator
22
External Crystal Oscillator
22
10-Bit Analog-To-Digital Converter
22
Analog Comparator
22
Timers
22
Interrupt Controller
22
Reset Controller
23
On-Chip Debugger
23
Acronyms and Expansions
23
Table 2. Acronyms and Expansions
23
Pin Description
24
Available Packages
24
Pin Configurations
24
Table 3. Z8 Encore! F0830 Series Package Options
24
Figure 2. Z8F0830 Series in 20-Pin SOIC, SSOP, PDIP Package
25
Figure 3. Z8F0830 Series in 28-Pin SOIC, SSOP, PDIP Package
25
Figure 4. Z8F0830 Series in 20-Pin QFN Package
26
Figure 5. Z8F0830 Series in 28-Pin QFN Package
27
Signal Descriptions
28
Table 4. Signal Descriptions
28
Pin Characteristics
30
Table 5. Pin Characteristics (20- and 28-Pin Devices)
30
Address Space
31
Register File
31
Program Memory
32
Table 6. Z8 Encore! F0830 Series Program Memory Maps
32
Data Memory
33
Flash Information Area
33
Table 7. Z8 Encore! F0830 Series Flash Memory Information Area Map
33
Table 8. Register File Address Map
34
Register Map
34
Reset and Stop Mode Recovery
38
Reset Types
38
Table 9. Reset and Stop Mode Recovery Characteristics and Latency
39
Reset Sources
40
Power-On Reset
40
Table 10. Reset Sources and Resulting Reset Type
40
Voltage Brown-Out Reset
41
Figure 6. Power-On Reset Operation
41
Watchdog Timer Reset
42
External Reset Input
42
Figure 7. Voltage Brown-Out Reset Operation
42
External Reset Indicator
43
On-Chip Debugger Initiated Reset
43
Stop Mode Recovery
43
Stop Mode Recovery Using WDT Time-Out
44
Stop Mode Recovery Using GPIO Port Pin Transition
44
Table 11. Stop Mode Recovery Sources and Resulting Action
44
Stop Mode Recovery Using the External RESET Pin
45
Debug Pin Driven Low
45
Reset Register Definitions
45
Table 12. por Indicator Values
46
Table 13. Reset Status Register (RSTSTAT)
46
Low-Power Modes
47
STOP Mode
47
HALT Mode
48
Peripheral Level Power Control
48
Power Control Register Definitions
48
Table 14. Power Control Register 0 (PWRCTL0)
49
General Purpose Input/Output
50
GPIO Port Availability by Device
50
Table 15. Port Availability by Device and Package Type
50
Architecture
51
GPIO Alternate Functions
51
Figure 8. GPIO Port Pin Block Diagram
51
Direct LED Drive
52
Shared Reset Pin
52
Crystal Oscillator Override
52
5 V Tolerance
52
External Clock Setup
53
Table 16. Port Alternate Function Mapping
53
GPIO Interrupts
56
GPIO Control Register Definitions
56
Table 17. GPIO Port Registers and Subregisters
56
Port A-D Address Registers
57
Table 18. Port A-D GPIO Address Registers (Pxaddr)
57
Table 19. Port Control Subregister Access
57
Port A-D Control Registers
58
Port A-D Data Direction Subregisters
58
Table 20. Port A-D Control Registers (Pxctl)
58
Table 21. Port A-D Data Direction Subregisters (Pxdd)
58
Port A-D Alternate Function Subregisters
59
Table 22. Port A-D Alternate Function Subregisters (Pxaf)
59
Table 23. Port A-D Output Control Subregisters (Pxoc)
60
Table 24. Port A-D High Drive Enable Subregisters (Pxhde)
61
Table 25. Port A-D Stop Mode Recovery Source Enable Subregisters (Pxsmre)
62
Table 26. Port A-D Pull-Up Enable Subregisters (Pxpue)
63
Table 27. Port A-D Alternate Function Set 1 Subregisters (Pxafs1)
64
Table 28. Port A-D Alternate Function Set 2 Subregisters (Pxafs2)
65
Port A-C Input Data Registers
66
Table 29. Port A-C Input Data Registers (Pxin)
66
Port A-D Output Data Register
67
Table 30. Port A-D Output Data Register (Pxout)
67
LED Drive Enable Register
68
LED Drive Level High Register
68
Table 31. LED Drive Enable (LEDEN)
68
Table 32. LED Drive Level High Register (LEDLVLH)
68
LED Drive Level Low Register
69
Table 33. LED Drive Level Low Register (LEDLVLL)
69
Interrupt Controller
70
Interrupt Vector Listing
70
Table 34. Trap and Interrupt Vectors in Order of Priority
71
Architecture
72
Operation
72
Master Interrupt Enable
72
Figure 9. Interrupt Controller Block Diagram
72
Interrupt Vectors and Priority
73
Interrupt Assertion
73
Software Interrupt Assertion
74
Interrupt Control Register Definitions
74
Interrupt Request 0 Register
75
Table 35. Interrupt Request 0 Register (IRQ0)
75
Interrupt Request 1 Register
76
Table 36. Interrupt Request 1 Register (IRQ1)
76
Interrupt Request 2 Register
77
IRQ0 Enable High and Low Bit Registers
77
Table 37. Interrupt Request 2 Register (IRQ2)
77
Table 38. IRQ0 Enable and Priority Encoding
77
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)
78
Table 40. IRQ0 Enable High Bit Register (IRQ0ENH)
78
IRQ1 Enable High and Low Bit Registers
79
Table 41. IRQ1 Enable and Priority Encoding
79
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)
79
IRQ2 Enable High and Low Bit Registers
80
Table 43. IRQ2 Enable and Priority Encoding
80
Table 44. IRQ1 Enable Low Bit Register (IRQ1ENL)
80
Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL)
81
Table 46. IRQ2 Enable High Bit Register (IRQ2ENH)
81
Interrupt Edge Select Register
82
Table 47. Interrupt Edge Select Register (IRQES)
82
Shared Interrupt Select Register
83
Table 48. Shared Interrupt Select Register (IRQSS)
83
Interrupt Control Register
84
Table 49. Interrupt Control Register (IRQCTL)
84
Timers
85
Architecture
85
Operation
86
Timer Operating Modes
86
Figure 10. Timer Block Diagram
86
Reading the Timer Count Values
99
Timer Pin Signal Operation
99
Timer Control Register Definitions
100
Timer 0-1 High and Low Byte Registers
100
Table 50. Timer 0-1 High Byte Register (Txh)
100
Table 51. Timer 0-1 Low Byte Register (Txl)
100
Timer Reload High and Low Byte Registers
102
Table 52. Timer 0-1 Reload High Byte Register (Txrh)
102
Table 53. Timer 0-1 Reload Low Byte Register (Txrl)
102
Timer 0-1 PWM High and Low Byte Registers
103
Table 54. Timer 0-1 PWM High Byte Register (Txpwmh)
103
Table 55. Timer 0-1 PWM Low Byte Register (Txpwml)
103
Timer 0-1 Control Registers
104
Table 56. Timer 0-1 Control Register 0 (Txctl0)
104
Table 57. Timer 0-1 Control Register 1 (Txctl1)
105
Watchdog Timer
109
Operation
109
Table 58. Watchdog Timer Approximate Time-Out Delays
109
Watchdog Timer Refresh
110
Watchdog Timer Time-Out Response
110
Watchdog Timer Reload Unlock Sequence
111
Watchdog Timer Control Register Definitions
112
Watchdog Timer Control Register
112
Table 59. Watchdog Timer Control Register (WDTCTL)
112
Watchdog Timer Reload Upper, High and Low Byte Registers
113
Table 60. Watchdog Timer Reload Upper Byte Register (WDTU)
113
Table 61. Watchdog Timer Reload High Byte Register (WDTH)
113
Table 62. Watchdog Timer Reload Low Byte Register (WDTL)
114
Analog-To-Digital Converter
115
Architecture
115
Operation
116
Figure 11. Analog-To-Digital Converter Block Diagram
116
ADC Timing
117
Figure 12. ADC Timing Diagram
117
Figure 13. ADC Convert Timing
117
ADC Interrupt
118
Calibration and Compensation
118
Internal Voltage Reference Generator
118
Reference Buffer
118
ADC Control Register Definitions
118
ADC Control Register 0
119
Table 63. ADC Control Register 0 (ADCCTL0)
119
ADC Data High Byte Register
120
ADC Data Low Bits Register
120
Table 64. ADC Data High Byte Register (ADCD_H)
120
Table 65. ADC Data Low Bits Register (ADCD_L)
120
Sample Settling Time Register
121
Table 66. Sample Settling Time (ADCSST)
121
Sample Time Register
122
Table 67. Sample Time (ADCST)
122
Comparator
123
Operation
123
Comparator Control Register Definitions
124
Table 68. Comparator Control Register (CMP0)
124
Flash Memory
125
Figure 14. 1K Flash with NVDS
125
Table 69. Z8 Encore! F0830 Series Flash Memory Configuration
125
Figure 15. 2K Flash with NVDS
126
Figure 16. 4K Flash with NVDS
126
Figure 17. 8K Flash with NVDS
127
Data Memory Address Space
128
Figure 18. 12K Flash Without NVDS
128
Flash Information Area
128
Operation
129
Table 70. Z8F083 Flash Memory Area Map
129
Figure 19. Flash Controller Operation Flow Chart
130
Flash Code Protection against Accidental Program and Erasure
131
Flash Code Protection against External Access
131
Flash Operation Timing Using the Flash Frequency Registers
131
Table 71. Flash Code Protection Using the Flash Option Bits
132
Byte Programming
133
Flash Controller Behavior in Debug Mode
134
Flash Controller Bypass
134
Mass Erase
134
Page Erase
134
Flash Control Register Definitions
135
Flash Control Register
136
Table 72. Flash Control Register (FCTL)
136
Flash Status Register
137
Table 73. Flash Status Register (FSTAT)
137
Flash Page Select Register
138
Table 74. Flash Page Select Register (FPS)
138
Flash Sector Protect Register
139
Table 75. Flash Sector Protect Register (FPROT)
139
Flash Frequency High and Low Byte Registers
140
Table 76. Flash Frequency High Byte Register (FFREQH)
140
Table 77. Flash Frequency Low Byte Register (FFREQL)
140
NVDS Operational Requirements
135
Flash Option Bits
141
Operation
141
Option Bit Configuration by Reset
141
Option Bit Types
142
Flash Option Bit Control Register Definitions
143
Trim Bit Address Register
143
Trim Bit Data Register
143
Table 78. Trim Bit Address Register (TRMADR)
143
Table 79. Trim Bit Address Map
143
Flash Option Bit Address Space
144
Table 80. Trim Bit Data Register (TRMDR)
144
Table 81. Flash Option Bits at Program Memory Address 0000H
144
Table 82. Flash Options Bits at Program Memory Address 0001H
145
Trim Bit Address Space
146
Table 85. Trim Bit Address Space
146
Table 83. Trim Option Bits at 0000H (ADCREF)
147
Table 84. Trim Option Bits at 0001H (TADC_COMP)
147
Table 86. Trim Option Bits at 0002H (TIPO)
148
Table 87. Trim Option Bits at 0003H (TVBO)
148
Table 88. VBO Trim Definition
149
Table 89. Trim Option Bits at 0006H (TCLKFLT)
149
Table 90. Clkflt Delay Control Definition
150
Nonvolatile Data Storage
151
Operation
151
NVDS Code Interface
151
Byte Write
152
Table 91. Write Status Byte
152
Byte Read
153
Table 92. Read Status Byte
153
Power Failure Protection
154
Optimizing NVDS Memory Usage for Execution Speed
154
Table 93. NVDS Read Time
154
On-Chip Debugger
156
Architecture
156
Figure 20. On-Chip Debugger Block Diagram
156
Operation
157
OCD Interface
157
Figure 21. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface
157
DEBUG Mode
158
Figure 22. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface
158
OCD Data Format
159
OCD Autobaud Detector/Generator
159
Figure 23. OCD Data Format
159
Table 94. OCD Baud-Rate Limits
159
OCD Serial Errors
160
Breakpoints
160
Runtime Counter
161
On-Chip Debugger Commands
161
Table 95. On-Chip Debugger Command Summary
161
On-Chip Debugger Control Register Definitions
165
OCD Control Register
165
Table 96. OCD Control Register (OCDCTL)
166
OCD Status Register
167
Table 97. OCD Status Register (OCDSTAT)
167
Oscillator Control
168
Operation
168
System Clock Selection
168
Table 98. Oscillator Configuration and Selection
169
Clock Failure Detection and Recovery
170
Oscillator Control Register Definitions
171
Table 99. Oscillator Control Register (OSCCTL)
171
Figure 24. Oscillator Control Clock Switching Flow Chart
173
Crystal Oscillator
174
Operating Modes
174
Crystal Oscillator Operation
174
Figure 25. Recommended 20 Mhz Crystal Oscillator Configuration
175
Table 100. Recommended Crystal Oscillator Specifications
175
Oscillator Operation with an External RC Network
176
Figure 26. Connecting the On-Chip Oscillator to an External RC Network
176
Figure 27. Typical RC Oscillator Frequency as a Function of External Capacitance
177
With a 45 Kω Resistor
177
Internal Precision Oscillator
178
Operation
178
Ez8 CPU Instruction Set
179
Assembly Language Programming Introduction
179
Assembly Language Syntax
180
Table 101. Assembly Language Syntax Example 1
180
Ez8 CPU Instruction Notation
181
Table 102. Assembly Language Syntax Example 2
181
Table 103. Notational Shorthand
181
Table 104. Additional Symbols
182
Ez8 CPU Instruction Classes
183
Table 105. Arithmetic Instructions
183
Table 106. Bit Manipulation Instructions
184
Table 107. Block Transfer Instructions
184
Table 108. CPU Control Instructions
185
Table 109. Load Instructions
185
Table 110. Rotate and Shift Instructions
186
Table 111. Logical Instructions
186
Table 112. Program Control Instructions
186
Ez8 CPU Instruction Summary
188
Table 113. Ez8 CPU Instruction Summary
188
Figure 28. Op Code Map Cell Description
197
Op Code Maps
197
Table 114. Op Code Map Abbreviations
198
Figure 29. First Op Code Map
199
Figure 30. Second Op Code Map after 1FH
200
Electrical Characteristics
201
Absolute Maximum Ratings
201
Table 115. Absolute Maximum Ratings
201
DC Characteristics
202
Table 116. DC Characteristics
202
Figure 31. ICC Versus System Clock Frequency (HALT Mode)
204
Figure 32. ICC Versus System Clock Frequency (NORMAL Mode)
205
AC Characteristics
206
Table 117. AC Characteristics
206
On-Chip Peripheral AC and DC Electrical Characteristics
207
Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics
207
Table 119. Flash Memory Electrical Characteristics and Timing
209
Table 120. Watchdog Timer Electrical Characteristics and Timing
209
Table 121. Nonvolatile Data Storage
210
Table 122. Analog-To-Digital Converter Electrical Characteristics and Timing
210
Table 123. Comparator Electrical Characteristics
211
Figure 33. Port Input Sample Timing
212
General Purpose I/O Port Input Data Sample Timing
212
Table 124. GPIO Port Input Timing
212
Figure 34. GPIO Port Output Timing
213
General Purpose I/O Port Output Timing
213
Table 125. GPIO Port Output Timing
213
Figure 35. On-Chip Debugger Timing
214
On-Chip Debugger Timing
214
Table 126. On-Chip Debugger Timing
214
Figure 36. Flash Current Diagram
215
Table 127. Power Consumption Reference Table
215
Packaging
216
Ordering Information
217
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
217
Part Number Suffix Designations
223
Table 129. Package and Pin Count Description
224
Appendix A. Register Tables
225
General Purpose RAM
225
Timer 0
225
Table 130. Timer 0 High Byte Register (T0H)
225
Table 131. Timer 0 Low Byte Register (T0L)
226
Table 132. Timer 0 Reload High Byte Register (T0RH)
226
Table 133. Timer 0 Reload Low Byte Register (T0RL)
226
Table 134. Timer 0 PWM High Byte Register (T0PWMH)
226
Table 135. Timer 0 PWM Low Byte Register (T0PWML)
227
Table 136. Timer 0 Control Register 0 (T0CTL0)
227
Table 137. Timer 0 Control Register 1 (T0CTL1)
227
Table 138. Timer 1 High Byte Register (T1H)
227
Table 139. Timer 1 Low Byte Register (T1L)
228
Table 140. Timer 1 Reload High Byte Register (T1RH)
228
Table 141. Timer 1 Reload Low Byte Register (T1RL)
228
Table 142. Timer 1 PWM High Byte Register (T1PWMH)
228
Table 143. Timer 1 PWM Low Byte Register (T1PWML)
229
Table 144. Timer 1 Control Register 0 (T1CTL0)
229
Table 145. Timer 1 Control Register 1 (T1CTL1)
229
Analog-To-Digital Converter
230
Table 146. ADC Control Register 0 (ADCCTL0)
230
Table 147. ADC Data High Byte Register (ADCD_H)
231
Table 148. ADC Data Low Bits Register (ADCD_L)
231
Table 149. ADC Sample Settling Time (ADCSST)
232
Table 150. ADC Sample Time (ADCST)
232
Low Power Control
233
LED Controller
233
Table 151. Power Control Register 0 (PWRCTL0)
233
Table 152. LED Drive Enable (LEDEN)
233
Oscillator Control
234
Table 153. LED Drive Level High Register (LEDLVLH)
234
Table 154. LED Drive Level Low Register (LEDLVLL)
234
Table 155. Oscillator Control Register (OSCCTL)
234
Comparator 0
235
Interrupt Controller
235
Table 156. Comparator Control Register (CMP0)
235
Table 157. Interrupt Request 0 Register (IRQ0)
235
Table 158. IRQ0 Enable High Bit Register (IRQ0ENH)
236
Table 159. IRQ0 Enable Low Bit Register (IRQ0ENL)
236
Table 160. Interrupt Request 1 Register (IRQ1)
236
Table 161. IRQ1 Enable High Bit Register (IRQ1ENH)
236
Table 162. IRQ1 Enable Low Bit Register (IRQ1ENL)
237
Table 163. Interrupt Request 2 Register (IRQ2)
237
Table 164. IRQ2 Enable High Bit Register (IRQ2ENH)
237
Table 165. IRQ2 Enable Low Bit Register (IRQ2ENL)
237
Table 166. Interrupt Edge Select Register (IRQES)
238
Table 167. Shared Interrupt Select Register (IRQSS)
238
Table 168. Interrupt Control Register (IRQCTL)
238
GPIO Port a
239
Table 169. Port a GPIO Address Register (PAADDR)
239
Table 170. Port a Control Registers (PACTL)
239
Table 171. Port a Input Data Registers (PAIN)
239
Table 172. Port a Output Data Register (PAOUT)
240
Table 173. Port B GPIO Address Register (PBADDR)
240
Table 174. Port B Control Registers (PBCTL)
240
Table 175. Port B Input Data Registers (PBIN)
240
Table 176. Port B Output Data Register (PBOUT)
241
Table 177. Port C GPIO Address Register (PCADDR)
241
Table 178. Port C Control Registers (PCCTL)
241
Table 179. Port C Input Data Registers (PCIN)
241
Table 180. Port C Output Data Register (PCOUT)
242
Table 181. Port D GPIO Address Register (PDADDR)
242
Table 182. Port D Control Registers (PDCTL)
242
Watchdog Timer
243
Table 183. Port D Output Data Register (PDOUT)
243
Table 184. Watchdog Timer Control Register (WDTCTL)
243
Table 185. Reset Status Register (RSTSTAT)
243
Table 186. Watchdog Timer Reload Upper Byte Register (WDTU)
244
Table 187. Watchdog Timer Reload High Byte Register (WDTH)
244
Table 188. Watchdog Timer Reload Low Byte Register (WDTL)
244
Trim Bit Control
245
Flash Memory Controller
245
Table 189. Trim Bit Address Register (TRMADR)
245
Table 190. Trim Bit Data Register (TRMDR)
245
Table 191. Flash Control Register (FCTL)
245
Table 192. Flash Status Register (FSTAT)
246
Table 193. Flash Page Select Register (FPS)
246
Table 194. Flash Sector Protect Register (FPROT)
246
Table 195. Flash Frequency High Byte Register (FFREQH)
246
Table 196. Flash Frequency Low Byte Register (FFREQL)
247
Index
248
Customer Support
256
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