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IXYS zilog Z80 User Manual

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Z80 Microprocessors
Z80 CPU
User Manual
UM008011-0816
Copyright ©2016 Zilog, Inc. All rights reserved.
www.zilog.com

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Summary of Contents for IXYS zilog Z80

  • Page 1 Z80 Microprocessors Z80 CPU User Manual UM008011-0816 Copyright ©2016 Zilog, Inc. All rights reserved. www.zilog.com...
  • Page 2 Z80 CPU User Manual DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. Warning: LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

  • Page 3: Revision History

    Z80 CPU User Manual Revision History Each instance in the following revision history table reflects a change to this document from its previous version. For more details, refer to the corresponding pages provided in the table. Revision Date Level Description Page Made formatting changes for better readability.
  • Page 4 Z80 CPU User Manual Revision History UM008011-0816...

  • Page 5: Table Of Contents

    Z80 CPU User Manual Table of Contents Revision History............iii Table of Contents .

  • Page 6: Table Of Contents

    Z80 CPU User Manual Addressing Modes ..........34 Immediate Addressing .
  • Page 7 Z80 CPU User Manual LD (IY+d), r ........... . 83 LD (HL), n .
  • Page 8 Z80 CPU User Manual viii LDIR ............132 LDD .
  • Page 9 Z80 CPU User Manual INC ss ............198 INC IX .
  • Page 10 Z80 CPU User Manual DJNZ, e ............278 CALL nn .

  • Page 11: List Of Figures

    Z80 CPU User Manual List of Figures Figure 1. Z80 CPU Block Diagram ........1 Figure 2.
  • Page 12 Z80 CPU User Manual Figure 29. Extended Addressing Mode ........36 Figure 30.
  • Page 13 Z80 CPU User Manual xiii List of Tables Table 1. Interrupt Enable/Disable, Flip-Flops ......18 Table 2.
  • Page 14 Z80 CPU User Manual List of Tables UM008011-0816...

  • Page 15: Architectural Overview

    Z80 CPU User Manual Architectural Overview Zilog’s Z80 CPU family of components are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second and third-generation microproces- sors. The speed offerings from 6–20 MHz suit a wide range of applications which migrate software.

  • Page 16: Cpu Register

    Z80 CPU User Manual CPU Register The Z80 CPU contains 208 bits of read/write memory that are available to the program- mer. Figure 2 shows how this memory is configured to eighteen 8-bit registers and four 16-bit registers. All Z80 CPU’s registers are implemented using static RAM. The registers include two sets of six general-purpose registers that can be used individually as 8-bit reg- isters or in pairs as 16-bit registers.

  • Page 17: General Purpose Registers

    Z80 CPU User Manual The two independent index registers hold a 16-bit base Two Index Registers (IX and IY). address that is used in indexed addressing modes. In this mode, an index register is used as a base to point to a region in memory from which data is to be stored or retrieved. An addi- tional byte is included in indexed instructions to specify a displacement from this base.

  • Page 18: Arithmetic Logic Unit

    Z80 CPU User Manual isters are used for a wide range of applications. They also simplify programing, specifi- cally in ROM-based systems in which little external read/write memory is available. Arithmetic Logic Unit The 8-bit arithmetic and logical instructions of the CPU are executed in the Arithmetic Logic Unit (ALU).

  • Page 19: Pin Functions

    Z80 CPU User Manual MREQ IORQ System Control RFSH Address HALT WAIT Z80 CPU Control RESET BUSRQ BUSACK Control Data Figure 3. Z80 CPU I/O Pin Configuration Pin Functions Address Bus (output, active High, tristate). A15–A0 form a 16-bit Address Bus, A15–A0.
  • Page 20 Z80 CPU User Manual RD, and WR have entered their high-impedance states. The external circuitry can now control these lines. Bus Request (input, active Low). Bus Request contains a higher priority than BUSREQ. NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to enter a high-impedance state so that other devices can control these lines.

  • Page 21: Timing

    Z80 CPU User Manual Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower RFSH. seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories. WAIT (input, active Low). WAIT communicates to the CPU that the addressed WAIT.

  • Page 22: Instruction Fetch

    Z80 CPU User Manual WAIT state is entered during the following cycle. Using this technique, the read can be lengthened to match the access time of any type of memory device. See the Input or Out- put Cycles section on page 10 to learn more about the automatic WAIT state. T Cycle Machine Cycle (Opcode Fetch)

  • Page 23: Memory Read Or Write

    Z80 CPU User Manual M1 Cycle A15 –A0 Refresh Address MREQ WAIT D7–D0 RFSH Figure 5. Instruction Op Code Fetch Memory Read Or Write Figure 6 shows the timing of memory read or write cycles other than an op code fetch cycle.

  • Page 24: Input Or Output Cycles

    Z80 CPU User Manual Memory Read Cycle Memory Write Cycle Memory Address Memory Address A15 –A0 MREQ D7–D0 Data Out WAIT Figure 6. Memory Read or Write Cycle Input or Output Cycles Figure 7 shows an I/O read or I/O write operation. During I/O operations, a single wait state is automatically inserted.

  • Page 25: Bus Request/Acknowledge Cycle

    Z80 CPU User Manual A15 –A0 Port Address IORQ Read Cycle D7–D0 WAIT Write Cycle D7–D0 Figure 7. Input or Output Cycles *In Figure 7, TW is an automatically-inserted WAIT state. Note: Bus Request/Acknowledge Cycle Figure 8 shows the timing for a Bus Request/Acknowledge cycle. The BUSREQ signal is sampled by the CPU with the rising edge of the most recent clock period of any machine cycle.

  • Page 26: Interrupt Request/Acknowledge Cycle

    Z80 CPU User Manual large blocks of data are transferred under DMA control. During a bus request cycle, the CPU cannot be interrupted by either an NMI or an INT signal. Bus Available Status Any M Cycle Last T State BUSREQ Sample Sample...

  • Page 27: Nonmaskable Interrupt Response

    Z80 CPU User Manual Last M Cycle of Instruction Last T State A15 –A0 Refresh MREQ IORQ D7–D0 WAIT Figure 9. Interrupt Request/Acknowledge Cycle Nonmaskable Interrupt Response Figure 10 shows the request/acknowledge cycle for the nonmaskable interrupt. This signal is sampled at the same time as the interrupt line, but this line takes priority over the normal interrupt and it cannot be disabled under software control.

  • Page 28: Halt Exit

    Z80 CPU User Manual Last M Cycle Last T State A15 –A0 Refresh MREQ RFSH Figure 10. Nonmaskable Interrupt Request Operation HALT Exit When a software HALT instruction is executed, the CPU executes NOPs until an interrupt is received (either a nonmaskable or a maskable interrupt while the interrupt flip-flop is enabled).

  • Page 29: Power-Down Acknowledge Cycle

    Z80 CPU User Manual HALT RD or Figure 11. HALT Exit The HALT instruction is repeated during the memory cycle shown in Figure 11. Note: Power-Down Acknowledge Cycle When the clock input to the Z80 CPU is stopped at either a High or Low level, the Z80 CPU stops its operation and maintains all registers and control signals.

  • Page 30: Power-Down Release Cycle

    Z80 CPU User Manual Power-Down Release Cycle The system clock must be supplied to the Z80 CPU to release the power-down state. When the system clock is supplied to the CLK input, the Z80 CPU restarts operations from the point at which the power-down state was implemented. The timing diagrams for the release from power-down mode are featured in Figures 13 through 15.

  • Page 31: Interrupt Response

    Z80 CPU User Manual HALT Figure 15. Power-Down Release Cycle, #3 of 3 Interrupt Response An interrupt allows peripheral devices to suspend CPU operation and force the CPU to start a peripheral service routine. This service routine usually involves the exchange of data, status, or control information between the CPU and the peripheral.

  • Page 32: Table 1. Interrupt Enable/Disable, Flip-Flops

    Z80 CPU User Manual The state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage location for IFF1. A CPU reset forces both the IFF1 and IFF2 to the reset state, which disables interrupts. Interrupts can be enabled at any time by an EI instruction from the programmer.

  • Page 33: Cpu Response

    Z80 CPU User Manual Table 1. Interrupt Enable/Disable, Flip-Flops (Continued) Action IFF1 IFF2 Comments Accept NMI Maskable → Interrupt. RETN Instruction IFF2 IFF2 → Indicates completion of Execution nonmaskable interrupt service routine. CPU Response The CPU always accepts a nonmaskable interrupt. When this nonmaskable interrupt is accepted, the CPU ignores the next instruction that it fetches and instead performs a restart at address .

  • Page 34: Figure 17. Mode 2 Interrupt Response Mode

    Z80 CPU User Manual In Mode 2, the programmer maintains a table of 16-bit starting addresses for every inter- rupt service routine. This table can be located anywhere in memory. When an interrupt is accepted, a 16-bit pointer must be formed to obtain the required interrupt service routine starting address from the table.

  • Page 35: Hardware And Software Implementation

    Z80 CPU User Manual Hardware and Software Implementation This chapter is an introduction to implementing systems that use the Z80 CPU. Figure 18 shows a simple Z80 system. +5V Power Supply –A Address MREQ 8K Bit Data Data Bus RESET IORQ CE RD IORQ...

  • Page 36: Adding Ram

    Z80 CPU User Manual Because the Z80 CPU requires only a single 5 V power supply, most small systems can be implemented using only this single supply. The external memory can be any mixture of standard RAM, ROM, or PROM. In Fig- ure 18, a single 8 Kb (1 KB) ROM comprises the entire memory system.

  • Page 37: Memory Speed Control

    Z80 CPU User Manual Address: 0000h 1 Kbyte ROM 03FFh 0400h 256 Bytes RAM 04FFFh Figure 20. RAM Memory Space Organization In Figure 20, the address space is portrayed in hexadecimal notation. Address bit A10 sep- arates the ROM space from the RAM space, allowing this address to be used for the chip select function.

  • Page 38: Figure 21. Adding One Wait State To An M1 Cycle

    Z80 CPU User Manual WAIT 7474 7474 WAIT Figure 21. Adding One Wait State to an M1 Cycle WAIT 7400 MREQ MREQ 7474 7474 WAIT Figure 22. Adding One Wait State to Any Memory Cycle Hardware and Software Implementation UM008011-0816...

  • Page 39: Interfacing Dynamic Memories

    Z80 CPU User Manual Interfacing Dynamic Memories Each individual dynamic RAM space includes its own specifications that require minor modifications to the examples provided here. Figure 23 shows the logic necessary to interface 8 KB of dynamic RAM using 18-pin 4K dynamic memories.

  • Page 40: Software Implementation Examples

    Z80 CPU User Manual Software Implementation Examples The Z80 instruction set provides the user with a large number of operations to control the Z80 CPU. The main alternate and index registers can hold arithmetic and logical opera- tions, form memory addresses, or act as fast-access storage for frequently used data. Information can be moved directly from register to register, memory to memory, memory to registers, or from registers to memory.

  • Page 41: Specific Z80 Instruction Examples

    Z80 CPU User Manual Specific Z80 Instruction Examples Example 1 When a 737-byte data string in memory location DATA must be moved to location BUF- FER, the operation is programmed as follows: HL, DATA ;START ADDRESS OF DATA STRING DE, BUFFER ;START ADDRESS OF TARGET BUFFER BC, 737 ;LENGTH OF DATA STRING...

  • Page 42: Figure 24. Shifting Of Bcd Digits/Bytes

    Z80 CPU User Manual HL, DATA ;ADDRESS OF FIRST BYTE B, COUNT ;SHIFT COUNT ;CLEAR ACCUMULATOR ROTAT: ;ROTATE LEFT low-order DIGIT IN ACC ;WITH DIGITS IN (HL) ;ADVANCE MEMORY POINTER. DJNZ ROTAT-$ ;DECREMENT B AND GO TO ROTAT IF ;B IS NOT ZERO, OTHERWISE FALL ;THROUGH Eleven bytes are required for this operation.

  • Page 43: Programming Task Examples

    Z80 CPU User Manual A, (HL) ;SUBTRACT (HL) FROM ACC ;ADJUST RESULT TO DECIMAL CODED VALUE (HL), A ;STORE RESULT ;ADVANCE MEMORY POINTERS DJNZ SUBDEC–$ ;DECREMENT B AND GO TO SUBDEC ;IF B ;NOT ZERO, OTHERWISE FALL ;THROUGH Seventeen bytes are required for this operation. Programming Task Examples As indicated in Table 2, this example program sorts an array of numbers to ascending order, using a standard exchange sorting algorithm.
  • Page 44 Z80 CPU User Manual Table 2. Bubble Listing (Continued) Object Location Code Statement Source Statement unused pointer into data array unused 0000 222600 sort: (data), hl ; save data address 0003 cb84 loop: flag, h ; initialize exchange flag 0005 b, c ;...

  • Page 45: Table 3. Multiply Listing

    Z80 CPU User Manual The program outlined in Table 3 multiplies two unsigned 16-bit integers, leaving the result in the HL register pair. Table 3. Multiply Listing Object Location Code Statement Source Statement 0000 mult:; unsigned sixteen bit integer multiply. on entrance: multiplier in de.

  • Page 46: Z80 Cpu Instructions

    Z80 CPU User Manual Z80 CPU Instructions The Z80 CPU can execute 158 different instruction types including all 78 of the 8080A CPU. The instructions fall into these major groups: Load and Exchange • Block Transfer and Search • Arithmetic and Logical •...
  • Page 47 Z80 CPU User Manual An example of an arithmetic operation is adding the Accumulator to the contents of an external memory location. The results of the addition are placed in the Accumulator. This group also includes 16-bit addition and subtraction between 16-bit CPU registers. The rotate and shift group allows any register or any memory location to be rotated right or left, with or without carry, and either arithmetic or logical.

  • Page 48: Addressing Modes

    Z80 CPU User Manual Addressing Modes Most of the Z80 instructions operate on data stored in internal CPU registers, external memory, or in the I/O ports. Addressing refers to how the address of this data is generated in each instruction. This section is a brief summary of the types of addressing used in the Z80 CPU while subsequent sections detail the type of addressing available for each instruction group.

  • Page 49: Modified Page Zero Addressing

    Z80 CPU User Manual Modified Page Zero Addressing The Z80 contains a special single-byte CALL instruction to any of eight locations in Page 0 of memory. This instruction, which is referred to as a restart, sets the Program Counter to an effective address in Page 0.

  • Page 50: Extended Addressing

    Z80 CPU User Manual Extended Addressing Extended Addressing provides for two bytes (16 bits) of address to be included in the instruction. This data can be an address to which a program can jump or it can be an address at which an operand is located. One or Op Code Two Bytes...

  • Page 51: Register Addressing

    Z80 CPU User Manual complement number. Indexed addressing greatly simplifies programs using tables of data because the index register can point to the start of any table. Two index registers are pro- vided because often operations require two or more tables. Indexed addressing also allows for relocatable code.

  • Page 52: Bit Addressing

    Z80 CPU User Manual parentheses around the name of the register that is to be used as the pointer. For example, the symbol (HL) specifies that the contents of the HL register are to be used as a pointer to a memory location.

  • Page 53: Instruction Notation Summary

    Z80 CPU User Manual Instruction Notation Summary Table 4 lists the operand notations and descriptions used in the Z80 Instruction Set. Table 4. Instruction Notation Summary Notation Description Identifies any of the registers A, B, C, D, E, H, or L Identifies the contents of the memory location, whose address is specified by (HL) the contents of the register pair HL...

  • Page 54: Instruction Op Codes

    Z80 CPU User Manual Instruction Op Codes This section describes each of the Z80 instructions and provides tables listing the op codes for every instruction. In each of these tables, the op codes in shaded areas are identical to those offered in the 8080A CPU. Also depicted is the assembly language mnemonic that is used for each instruction.

  • Page 55: Load And Exchange

    Z80 CPU User Manual Load and Exchange Table 6 defines the op codes for all of the 8-bit load instructions implemented in the Z80 CPU. Also described in this table is the type of addressing used for each instruction. The source of the data is found on the top horizontal row and the destination is specified in the left column.

  • Page 56: Table 6. 8-Bit Load Group Ld

    Z80 CPU User Manual Table 6. 8-Bit Load Group LD Source Implied Register Reg Indirect Indexed Ext. Imm. Destination (HL) (BC) (DE) (IX+d) (lY+d) (nn) Register Register (HL) Indirect (BC) (DE) Indexed (IX+d) (IY+d) Ext. Addr. (nn) Implied Z80 CPU Instructions UM008011-0816...

  • Page 57: Figure 32. Example Of A 3-Byte Load Indexed Instruction Sequence

    Z80 CPU User Manual Descriptions of the 8-Bit Load Group instructions begin on page 70. Note: The parentheses around the HL indicate that the contents of HL are used as a pointer to a memory location. In all Z80 load instruction mnemonics, the destination is always listed first, with the source following.

  • Page 58: Figure 33. Example Of A 3-Byte Load Extended Instruction Sequence

    Z80 CPU User Manual Op Code Address A low-order Address high-order Address Figure 33. Example of a 3-Byte Load Extended Instruction Sequence In this figure, note that the low-order portion of the address is always the first operand. The load immediate instructions for the general-purpose 8-bit registers are two-byte instructions.

  • Page 59: Table 7. 16-Bit Load Group Ld, Push, And Pop

    Z80 CPU User Manual In this figure, note that with any indexed addressing, the displacement always follows directly after the op code. Table 7 specifies the 16-bit load operations, for which the extended addressing feature covers all register pairs. Register indirect operations specifying the stack pointer are the PUSH and POP instructions.

  • Page 60: Figure 36. Example Of A 16-Bit Load Operation

    Z80 CPU User Manual Descriptions of the 16-Bit Load Group instructions begin on page 98. Note: These 16-bit load operations differ from other 16-bit loads in that the stack pointer is auto- matically decremented and incremented as each byte is pushed onto or popped from the stack, respectively.

  • Page 61: Block Transfer And Search

    Z80 CPU User Manual Address A Op Code Operand Figure 37. Example of a 2-Byte Load Indexed/Immediate Instruction Sequence In all extended immediate or extended addressing modes, the low-order byte always appears first after the op code. Table 8 lists the 16-bit exchange instructions implemented in the Z80 CPU. Op code allows the programmer to switch between the two pairs of Accumulator flag registers, while allows the programmer to switch between the duplicate set of six general-pur-...

  • Page 62: Table 9. Block Transfer Group

    Z80 CPU User Manual Table 9. Block Transfer Group Destination Source Register (DE) Register Indirect Indirect (HL) (ED) LDI – Load (DE) → (HL) Inc HL and DE, Dec BC (ED) LDIR, – Load (DE) → (HL) Inc HL and DE, Dec BC; repeat until BC = 0. (ED) LDD –...

  • Page 63: Arithmetic And Logical

    Z80 CPU User Manual Table 10. Block Search Group Search Location Register Indirect (HL) (ED) Inc HL, Dec BC (ED) CPRI. Inc HL, Dec BC Repeat until) BC = 0 or find match (ED) WD Dec HL and BC (ED) CPDR Dec HL and BC Repeat until BC = 0 or find match Note: HL points to a location in memory to be compared with...

  • Page 64: Table 11. 8-Bit Arithmetic And Logic

    Z80 CPU User Manual Table 11. 8-Bit Arithmetic and Logic Source Register Register Addressing Indirect Indexed Immediate Destination (HL) (IX+d) (lY+d) Add with Carry Subtract Subtract with Carry Compare Increment Decrement Descriptions of the 8-Bit Arithmetic Group instructions begin on page 144. Note: The result of the operation is placed in the Accumulator with the exception of the compare (CP) instruction, which leaves the Accumulator unchanged.

  • Page 65: Figure 38. Example Of An And Instruction Sequence

    Z80 CPU User Manual The INC and DEC instructions specify a register or a memory location as both the source and the destination of the result. When the source operand is addressed using the index registers, the displacement must directly follow. With immediate addressing, the actual operand directly follows.

  • Page 66: Table 13. 16-Bit Arithmetic

    Z80 CPU User Manual Descriptions of the General-Purpose Arithmetic and CPU Control Groups instructions Note: begin on page 172. The decimal adjust instruction can adjust for subtraction and addition, making BCD arith- metic operations simple. 1. To allow for this operation, the N flag is used. This flag is set if the most recent arithmetic Notes: operation was a Subtract.

  • Page 67: Rotate And Shift

    Z80 CPU User Manual Rotate and Shift A major feature of the Z80 CPU is to rotate or shift data in the Accumulator, any general- purpose register, or any memory location. All of the Rotate and Shift op codes are depicted in Figure 39.

  • Page 68: Figure 39. Rotates And Shifts

    Z80 CPU User Manual Source Type Rotate Shift L (HL) (IX+d) (lY+d) Rotate Left Circular RLCA 07 Rotate Right Circular Rotate RRCA 0F Left Rotate Right Shift Left Arithmetic Shift Right Arithmetic Shift Right Logical Rotate –b –b Digit –b (HL) Left Rotate...

  • Page 69: Bit Manipulation

    Z80 CPU User Manual Bit Manipulation The ability to set, reset, and test individual bits in a register or memory location is required in almost every program. These bits can be flags in a general-purpose software routine, indications of external control conditions, or data packed into memory locations, making memory utilization more efficient.
  • Page 70 Z80 CPU User Manual Table 14. Bit Manipulation Group (Continued) Register Register Addressing Indirect Indexed Test Bit (cont’d.) Rest Bit Z80 CPU Instructions UM008011-0816...
  • Page 71 Z80 CPU User Manual Table 14. Bit Manipulation Group (Continued) Register Register Addressing Indirect Indexed Rest Bit (cont’d.) Set Bit UM008011-0816 Bit Manipulation...

  • Page 72: Jump, Call, And Return

    Z80 CPU User Manual Register addressing can specify the Accumulator or any general-purpose register on which an operation is to be performed. Register Indirect and Indexed addressing are available for operations at external memory locations. Bit test operations set the Zero flag (Z) if the tested bit is a 0.

  • Page 73: Table 15. Jump, Call, And Return Group

    Z80 CPU User Manual Table 15. Jump, Call, and Return Group Condition Non- Non- Parity Parity Sign Sign Cond. Carry Carry Zero Zero Even B¹0 JUMP IMMED. EXT. JUMP RELATIVE PC+e e–2 e–2 e–2 e–2 e–2 (HL) JUMP Register (IX) INDIR.

  • Page 74: Table 16. Example Usage Of The Djnz Instruction

    Z80 CPU User Manual gram Counter to form a jump address. The call and return instructions allow for simple subroutine and interrupt handling. Two special return instruction are included in the Z80 family of microprocessors. The return from interrupt instruction (RETI) and the return from nonmaskable interrupt (RETN) are treated in the CPU as an unconditional return identical to the op code C9h.

  • Page 75: Input/Output

    Z80 CPU User Manual Table 17. Restart Group Op Code 0000h RST 0 0008h RST 8 0010h RST 16 0018h RST 24 CALL Address 0020h RST 32 0028h RST 40 0030h RST 48 0038h RST 56 Descriptions of the Call and Return Group instructions begin on page 280.

  • Page 76: Table 18. Input Group

    Z80 CPU User Manual Table 18. Input Group Register Immediate Indirect) Input Register Address Input Destination INI: input & inc HL, Dec B INIR: INP, Inc HL, Block Dec B, repeat if B≠0 Register (HL) Input Indir IND: input & Inc Commands Dec HL, Dec B INDR: input, Dec HL,...

  • Page 77: Cpu Control Group

    Z80 CPU User Manual Table 19. 8-Bit Arithmetic and Logic Source Register Register Indirect (HL) Immediate 11OUT 11OUT: output Block inc HL, dec B Output Command 11OUT: output Register dec B, repeat if B≠0 Indirect 11OUT: output dec HL and B 11OUTDR: output, dec HL and B, repeat if B≠0...

  • Page 78: Figure 41. Mode 2 Interrupt Command

    Z80 CPU User Manual Table 20. Miscellaneous CPU Control HALT Disable INT (EI) Enable INT (EI) Set INT Mode 0 8080A mode Set INT Mode 1 Call to address 0038h Set INT Mode 2 Indirect call using Register I and B bits from INTER device as a pointer If Mode 0 is set, the interrupting device can insert any instruction on the data bus and allow the CPU to execute it.

  • Page 79: Z80 Instruction Set

    Z80 CPU User Manual Z80 Instruction Set This chapter provides a description of the assembly language instructions available with the Z80 CPU. Z80 Assembly Language Assembly language allows the user to write a program without concern for memory addresses or machine instruction formats. It uses symbolic addresses to identify memory locations and mnemonic codes (op codes and operands) to represent the instructions.

  • Page 80: Carry Flag

    Z80 CPU User Manual Table 22. Flag Definitions Symbol Field Name Carry Flag Add/Subtract Parity/Overflow Flag Half Carry Flag Zero Flag Sign Flag Not Used Each of these two Flag registers contains 6 bits of status information that are set or cleared by CPU operations;...

  • Page 81: Decimal Adjust Accumulator Flag

    Z80 CPU User Manual Decimal Adjust Accumulator Flag The Decimal Adjust Accumulator (DAA) instruction uses this flag to distinguish between ADD and SUBTRACT instructions. For all ADD instructions, N sets to 0. For all SUB- TRACT instructions, N sets to 1. Parity/Overflow Flag The Parity/Overflow (P/V) Flag is set to a specific state depending on the operation being performed.

  • Page 82: Half Carry Flag

    Z80 CPU User Manual During the CPI, CPIR, CPD, and CPDR search instructions and the LDI, LDIR, LDD, and LDDR block transfer instructions, the P/V Flag monitors the state of the Byte Count (BC) Register. When decrementing, if the byte counter decrements to 0, the flag is cleared to 0; otherwise the flag is set to1.

  • Page 83: Sign Flag

    Z80 CPU User Manual Sign Flag The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When the Z80 CPU performs arithmetic operations on signed numbers, the binary twos- complement notation is used to represent and process numeric information. A positive number is identified by a 0 in Bit 7.
  • Page 84 Z80 CPU User Manual 8-Bit Load Group The following 8-bit load instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. LD r, r' – see page 71 LD r,n – see page 72 LD r, (HL) –...

  • Page 85: Ld R, R

    Z80 CPU User Manual LD r, r' Operation r, ← r′ Op Code Operands r, r′ Description The contents of any register r' are loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register r, C M Cycles...

  • Page 86: Ld R,N

    Z80 CPU User Manual LD r,n Operation r ← n Op Code Operands r, n Description The 8-bit integer n is loaded to any register r, in which r identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles T States...
  • Page 87 Z80 CPU User Manual Example Upon the execution of an LD E, instruction, Register E contains UM008011-0816 Z80 Instruction Description...

  • Page 88: Ld R, (Hl)

    Z80 CPU User Manual LD r, (HL) Operation r ← (HL) Op Code Operands r, (HL) Description The 8-bit contents of memory location (HL) are loaded to register r, in which r identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles T States...

  • Page 89: Ld R, (Ix+D)

    Z80 CPU User Manual LD r, (IX+d) Operation r ← (IX+d) Op Code Operands r, (IX+d) Description The (IX+d) operand (i.e., the contents of Index Register IX summed with two’s-comple- ment displacement integer d) is loaded to register r, in which r identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles...
  • Page 90 Z80 CPU User Manual Example If Index Register IX contains the number , the instruction LD B, (IX+19h) allows 25AFh the calculation of the sum , which points to memory location . If this 25AFh 25C8h address contains byte , the instruction results in Register B also containing Z80 Instruction Set UM008011-0816...

  • Page 91: Ld R, (Iy+D)

    Z80 CPU User Manual LD r, (IY+d) Operation r ← (IY+D) Op Code Operands r, (lY+d) Description The operand (lY+d) loads the contents of Index Register IY summed with two’s-comple- ment displacement integer, d, to register r, in which r identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles...
  • Page 92 Z80 CPU User Manual Example If Index Register IY contains the number , the instruction LD B, (IY+19h) allows 25AFh the calculation of the sum , which points to memory location . If this 25AFh 25C8h address contains byte , the instruction results in Register B also containing Z80 Instruction Set UM008011-0816...

  • Page 93: Ld (Hl), R

    Z80 CPU User Manual LD (HL), r Operation (HL) ← r Op Code Operands (HL), r Description The contents of register r are loaded to the memory location specified by the contents of the HL register pair. The r symbol identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles...
  • Page 94 Z80 CPU User Manual Example If the contents of register pair HL specify memory location and Register B contains 2146h byte , then upon the execution of an LD (HL), B instruction, memory address 2146h also contains Z80 Instruction Set UM008011-0816...

  • Page 95: Ld (Ix+D), R

    Z80 CPU User Manual LD (IX+d), r Operation (IX+d) ← r Op Code Operands (IX+d), r Description The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d, a two’s-complement displacement integer. The r sym- bol identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles...
  • Page 96 Z80 CPU User Manual Example If the C register contains byte , and Index Register IX contains , then the 3100h instruction LID (IX + ), C performs the sum and loads to memory 3100h location 3106h Z80 Instruction Set UM008011-0816...

  • Page 97: Ld (Iy+D), R

    Z80 CPU User Manual LD (IY+d), r Operation (lY+d) ← r Op Code Operands (lY+d), r Description The contents of resister r are loaded to the memory address specified by the sum of the contents of Index Register IY and d, a two’s-complement displacement integer. The r sym- bol is specified according to the following table.
  • Page 98 Z80 CPU User Manual Example If the C register contains byte , and Index Register IY contains , then the 2A11h instruction LD (IY + ), C performs the sum , and loads to memory 2A11h location 2A15 Z80 Instruction Set UM008011-0816...

  • Page 99: Ld (Hl), N

    Z80 CPU User Manual LD (HL), n Operation (HL) ← n Op Code Operands (HL), n Description The n integer is loaded to the memory address specified by the contents of the HL register pair. M Cycles T States 4 MHz E.T. 10 (4, 3, 3) 2.50 Condition Bits Affected...

  • Page 100: Ld (Ix+D), N

    Z80 CPU User Manual LD (IX+d), n Operation (IX+d) ← n Op Code Operands (IX+d), n Description The n operand is loaded to the memory address specified by the sum of Index Register IX and the two’s complement displacement operand d. M Cycles T States 4 MHz E.T.

  • Page 101: Ld (Iy+D), N

    Z80 CPU User Manual LD (IY+d), n Operation (lY+d) ← n Op Code Operands (lY+d), n Description The n integer is loaded to the memory location specified by the contents of Index Register summed with the two’s-complement displacement integer, d. M Cycles T States 4 MHz E.T.

  • Page 102: Ld A, (Bc)

    Z80 CPU User Manual LD A, (BC) Operation A ← (BC) Op Code Operands A, (BC) Description The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator. M Cycles T States 4 MHz E.T.

  • Page 103: Ld A, (De)

    Z80 CPU User Manual LD A, (DE) Operation A ← (DE) Op Code Operands A, (DE) Description The contents of the memory location specified by the register pair DE are loaded to the Accumulator. M Cycles T States 4 MHz E.T. 7 (4, 3) 1.75 Condition Bits Affected...

  • Page 104: Ld A, (Nn)

    Z80 CPU User Manual LD A, (nn) Operation A ← (nn) Op Code Operands A, (nn) Description The contents of the memory location specified by the operands nn are loaded to the Accu- mulator. The first n operand after the op code is the low-order byte of a 2-byte memory address.

  • Page 105: Ld (Bc), A

    Z80 CPU User Manual LD (BC), A Operation (BC) ← A Op Code Operands (BC), A Description The contents of the Accumulator are loaded to the memory location specified by the con- tents of the register pair BC. M Cycles T States 4 MHz E.T.

  • Page 106: Ld (De), A

    Z80 CPU User Manual LD (DE), A Operation (DE) ← A Op Code Operands (DE), A Description The contents of the Accumulator are loaded to the memory location specified by the con- tents of the DE register pair. M Cycles T States 4 MHz E.T.

  • Page 107: Ld (Nn), A

    Z80 CPU User Manual LD (nn), A Operation (nn) ← A Op Code Operands (nn), A Description The contents of the Accumulator are loaded to the memory address specified by the oper- and nn. The first n operand after the op code is the low-order byte of nn. M Cycles T States 4 MHz E.T.

  • Page 108: Ld A, I

    Z80 CPU User Manual LD A, I Operation A ← 1 Op Code Operands A, I Description The contents of the Interrupt Vector Register I are loaded to the Accumulator. M Cycles T States MHz E.T. 9 (4, 5) 2.25 Condition Bits Affected S is set if the I Register is negative;...

  • Page 109: Ld A, R

    Z80 CPU User Manual LD A, R Operation A ← R Op Code Operands A, R Description The contents of Memory Refresh Register R are loaded to the Accumulator. M Cycles T States MHz E.T. 9 (4, 5) 2.25 Condition Bits Affected S is set if, R-Register is negative;...

  • Page 110: Ld I,A

    Z80 CPU User Manual LD I,A Operation I ← A Op Code Operands I, A Description The contents of the Accumulator are loaded to the Interrupt Control Vector Register, I. M Cycles T States MHz E.T. 9 (4, 5) 2.25 Condition Bits Affected None.

  • Page 111: Ld R, A

    Z80 CPU User Manual LD R, A Operation R ← A Op Code Operands R, A Description The contents of the Accumulator are loaded to the Memory Refresh register R. M Cycles T States MHz E.T. 9 (4, 5) 2.25 Condition Bits Affected None.
  • Page 112 Z80 CPU User Manual 16-Bit Load Group The following 16-bit load instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. LD dd, nn – see page 99 LD IX, nn – see page 100 LD IY, nn –...

  • Page 113: Ld Dd, Nn

    Z80 CPU User Manual LD dd, nn Operation dd ← nn Op Code Operands dd, nn Description The 2-byte integer nn is loaded to the dd register pair, in which dd defines the BC, DE, HL, or SP register pairs, assembled as follows in the object code: Pair The first n operand after the op code is the low-order byte.

  • Page 114: Ld Ix, Nn

    Z80 CPU User Manual LD IX, nn Operation IX ← nn Op Code Operands IX, nn Description The n integer is loaded to Index Register IX. The first n operand after the op code is the low-order byte. M Cycles T States 4 MHz E.T.

  • Page 115: Ld Iy, Nn

    Z80 CPU User Manual LD IY, nn Operation IY ← nn Op Code Operands IY, nn Description The nn integer is loaded to Index Register IY. The first n operand after the op code is the low-order byte. M Cycles T States 4 MHz E.T.

  • Page 116: Ld Hl, (Nn)

    Z80 CPU User Manual LD HL, (nn) Operation H ← (nn + 1), L ← (nn) Op Code Operands HL, (nn) Description The contents of memory address (nn) are loaded to the low-order portion of register pair HL (Register L), and the contents of the next highest memory address (nn + 1) are loaded to the high-order portion of HL (Register H).

  • Page 117: Ld Dd, (Nn)

    Z80 CPU User Manual LD dd, (nn) Operation ddh ← (nn + 1) ddl ← (nn) Op Code Operands dd, (nn) Description The contents of address (nn) are loaded to the low-order portion of register pair dd, and the contents of the next highest memory address (nn + 1) are loaded to the high-order portion of dd.
  • Page 118 Z80 CPU User Manual Example If Address contains and address contains , then upon the execution 2130h 2131h of an LD BC, ( ) instruction, the BC register pair contains 2130h 7865h Z80 Instruction Set UM008011-0816...

  • Page 119: Ld Ix, (Nn)

    Z80 CPU User Manual LD IX, (nn) Operation IXh ← (nn + 1), IXI ← (nn) Op Code Operands IX, (nn) Description The contents of the address (nn) are loaded to the low-order portion of Index Register IX, and the contents of the next highest memory address (nn + 1) are loaded to the high-order portion of IX.

  • Page 120: Ld Iy, (Nn)

    Z80 CPU User Manual LD IY, (nn) Operation IYh ← (nn + 1), IYI ← nn) Op Code Operands IY, (nn) Description The contents of address (nn) are loaded to the low-order portion of Index Register IY, and the contents of the next highest memory address (nn + 1) are loaded to the high-order por- tion of IY.

  • Page 121: Ld (Nn), Hl

    Z80 CPU User Manual LD (nn), HL Operation (nn + 1) ← H, (nn) ← L Op Code Operands (nn), HL Description The contents of the low-order portion of register pair HL (Register L) are loaded to mem- ory address (nn), and the contents of the high-order portion of HL (Register H) are loaded to the next highest memory address (nn + 1).

  • Page 122: Ld (Nn), Dd

    Z80 CPU User Manual LD (nn), dd Operation (nn + 1) ← ddh, (nn) ← ddl Op Code Operands (nn), dd Description The low-order byte of register pair dd is loaded to memory address (nn); the upper byte is loaded to memory address (nn + 1). Register pair dd defines either BC, DE, HL, or SP, assembled as follows in the object code: Pair The first n operand after the op code is the low-order byte of a two byte memory address.
  • Page 123 Z80 CPU User Manual Example If register pair BC contains the number , the instruction , BC results in 4644h LD (1000h) in memory location , and in memory location 1000h 1001h UM008011-0816 Z80 Instruction Description...

  • Page 124: Ld (Nn), Ix

    Z80 CPU User Manual LD (nn), IX Operation (nn + 1) ← IXh, (nn) ← IXI Op Code Operands (nn), IX Description The low-order byte in Index Register IX is loaded to memory address (nn); the upper order byte is loaded to the next highest address (nn + 1). The first n operand after the op code is the low-order byte of nn.

  • Page 125: Ld (Nn), Iy

    Z80 CPU User Manual LD (nn), IY Operation (nn + 1) ← IYh, (nn) ← IYI Op Code Operands (nn), IY Description The low-order byte in Index Register IY is loaded to memory address (nn); the upper order byte is loaded to memory location (nn + 1). The first n operand after the op code is the low- order byte of nn.

  • Page 126: Ld Sp, Hl

    Z80 CPU User Manual LD SP, HL Operation SP ← HL Op Code Operands SP, HL Description The contents of the register pair HL are loaded to the Stack Pointer (SP). M Cycles T States 4 MHz E.T. Condition Bits Affected None.

  • Page 127: Ld Sp, Ix

    Z80 CPU User Manual LD SP, IX Operation ← Op Code Operands SP, IX Description The 2-byte contents of Index Register IX are loaded to the Stack Pointer (SP). M Cycles T States 4 MHz E.T. 10 (4, 6) 2.50 Condition Bits Affected None.

  • Page 128: Ld Sp, Iy

    Z80 CPU User Manual LD SP, IY Operation SP ← IY Op Code Operands SP, IY Description The 2-byte contents of Index Register IY are loaded to the Stack Pointer SP. M Cycles T States 4 MHz E.T. 10 (4, 6) 2.50 Condition Bits Affected None.

  • Page 129: Push Qq

    Z80 CPU User Manual PUSH qq Operation (SP – 2) ← qqL, (SP – 1) ← qqH Op Code PUSH Operand Description The contents of the register pair qq are pushed to the external memory last-in, first-out (LIFO) stack. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack.
  • Page 130 Z80 CPU User Manual Example If the AF Register pair contains and the Stack Pointer contains , then upon 2233h 1007h the execution of a PUSH AF instruction, memory address contains , memory 1006h address contains , and the Stack Pointer contains 1005h 1005h Z80 Instruction Set...

  • Page 131: Push Ix

    Z80 CPU User Manual PUSH IX Operation (SP – 2) ← IXL, (SP – 1) ← IXH Op Code PUSH Operand Description The contents of Index Register IX are pushed to the external memory last-in, first-out (LIFO) stack. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack.

  • Page 132: Push Iy

    Z80 CPU User Manual PUSH IY Operation (SP – 2) ← IYL, (SP – 1) ← IYH Op Code PUSH Operand Description The contents of Index Register IY are pushed to the external memory last-in, first-out (LIFO) stack. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack.

  • Page 133: Pop Qq

    Z80 CPU User Manual POP qq Operation qqH ← (SP+1), qqL ← (SP) Op Code Operand Description The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to reg- ister pair qq. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack.
  • Page 134 Z80 CPU User Manual Example If the Stack Pointer contains , memory location contains , and location 1000h 1000h contains , the instruction POP HL results in register pair HL containing 1001h 3355h and the Stack Pointer containing 1002h Z80 Instruction Set UM008011-0816...

  • Page 135: Pop Ix

    Z80 CPU User Manual POP IX Operation IXH ← (SP+1), IXL ← (SP) Op Code Operand Description The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to Index Register IX. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack.

  • Page 136: Pop Iy

    Z80 CPU User Manual POP IY Operation IYH ← (SP – X1), IYL ← (SP) Op Code Operand Description The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to Index Register IY. The Stack Pointer (SP) Register pair holds the 16-bit address of the cur- rent top of the Stack.
  • Page 137 Z80 CPU User Manual Exchange, Block Transfer, and Search Group The following exchange, block transfer, and search group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. EX DE, HL – see page 124 EX AF, AF′...

  • Page 138: Ex De, Hl

    Z80 CPU User Manual EX DE, HL Operation ↔ Op Code Operands DE, HL Description The 2-byte contents of register pairs DE and HL are exchanged. M Cycles T States 4 MHz E.T. 1.00 Condition Bits Affected None. Example If register pair DE contains and register pair HL contains , then upon the 2822h...

  • Page 139: Ex Af, Af

    Z80 CPU User Manual EX AF, AF′ Operation ↔ Op Code Operands AF, AF′ Description The 2-byte contents of the register pairs AF and AF' are exchanged. Register pair AF con- sists of registers A′ and F′. M Cycles T States 4 MHz E.T.

  • Page 140: Exx

    Z80 CPU User Manual Operation (BC) ↔ (BC′), (DE) ↔ (DE'), (HL) ↔ (HL′) Op Code Operands None. Description Each 2-byte value in register pairs BC, DE, and HL is exchanged with the 2-byte value in BC', DE', and HL', respectively. M Cycles T States 4 MHz E.T.

  • Page 141: Ex (Sp), Hl

    Z80 CPU User Manual EX (SP), HL Operation ↔ ↔ (SP+1), L (SP) Op Code Operands (SP), HL Description The low-order byte contained in register pair HL is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), and the high- order byte of HL is exchanged with the next highest memory address (SP+1).

  • Page 142: Ex (Sp), Ix

    Z80 CPU User Manual EX (SP), IX Operation ↔ ↔ (SP+1), IXL (SP) Op Code Operands (SP), IX Description The low-order byte in Index Register IX is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), and the high-order byte of IX is exchanged with the next highest memory address (SP+1).

  • Page 143: Ex (Sp), Iy

    Z80 CPU User Manual EX (SP), IY Operation ↔ ↔ (SP+1), IYL (SP) Op Code Operands (SP), IY Description The low-order byte in Index Register IY is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), and the high-order byte of IY is exchanged with the next highest memory address (SP+1).

  • Page 144: Ldi

    Z80 CPU User Manual Operation (DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC ← BC – 1 Op Code Operands None Description A byte of data is transferred from the memory location addressed, by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair.
  • Page 145 Z80 CPU User Manual register pair contains , then the instruction results in the following contents in reg- ister pairs and memory addresses: contains 1112h (1111h) contains contains 2223h (2222h) contains contains UM008011-0816 Z80 Instruction Description...

  • Page 146: Ldir

    Z80 CPU User Manual LDIR Operation repeat {(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC ← BC – 1} while (BC ≠ 0) Op Code LDIR Operand None Description This 2-byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the DE register pair.
  • Page 147 Z80 CPU User Manual P/V is set if BC – 1 ≠ 0; otherwise, it is reset. N is reset. C is not affected. Example The HL register pair contains , the DE register pair contains , the BC regis- 11111h 2222h ter pair contains...

  • Page 148: Ldd

    Z80 CPU User Manual Operation (DE) ← (HL), DE ← DE – 1, HL ← HL– 1, BC ← BC– 1 Op Code Operands None. Description This 2-byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair.
  • Page 149 Z80 CPU User Manual ister pair contains , then instruction LDD results in the following contents in register pairs and memory addresses: contains 1110h (1111h) contains contains 2221h (2222h) contains contains UM008011-0816 Z80 Instruction Description...

  • Page 150: Lddr

    Z80 CPU User Manual LDDR Operation (DE) ← (HL), DE ← DE – 1, HL ← HL – 1, BC ← BC – 1 Op Code LDDR Operands None. Description This 2-byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair.
  • Page 151 Z80 CPU User Manual Condition Bits Affected S is not affected. Z is not affected. H is reset. P/V is reset. N is reset. Example The HL register pair contains , the DE register pair contains , the BC register 1114h 2225h pair contains...

  • Page 152: Cpi

    Z80 CPU User Manual Operation A – (HL), HL ← HL +1, BC ← BC – 1 Op Code Operands None. Description The contents of the memory location addressed by the HL register is compared with the contents of the Accumulator. With a true compare, a condition bit is set. Then HL is incre- mented and the Byte Counter (register pair BC) is decremented.

  • Page 153: Cpir

    Z80 CPU User Manual CPIR Operation A – (HL), HL ← HL+1, BC ← BC – 1 Op Code CPIR Operands None. Description The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. HL is incremented and the Byte Counter (register pair BC) is decremented.
  • Page 154 Z80 CPU User Manual Condition Bits Affected S is set if result is negative; otherwise, it is reset. Z is set if A equals (HL); otherwise, it is reset. H is set if borrow from bit 4; otherwise, it is reset. P/V is set if BC –...

  • Page 155: Cpd

    Z80 CPU User Manual Operation A – (HL), HL ← HL – 1, BC ← BC – 1 Op Code Operands None. Description The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. The HL and Byte Counter (register pair BC) are decremented.

  • Page 156: Cpdr

    Z80 CPU User Manual CPDR Operation A – (HL), HL ← HL – 1, BC ← BC – 1 Op Code CPDR Operands None. Description The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator.
  • Page 157 Z80 CPU User Manual P/V is set if BC – 1 ≠ 0; otherwise, it is reset. N is set. C is not affected. Example The HL register pair contains , the Accumulator contains , the Byte Counter 1118h contains , and memory locations contain the following data.
  • Page 158 Z80 CPU User Manual 8-Bit Arithmetic Group The following 8-bit arithmetic group instructions are each described in this section. Sim- ply click to jump to an instruction’s description to learn more. ADD A, r – see page 145 ADD A, n –...

  • Page 159: Add A, R

    Z80 CPU User Manual ADD A, r Operation A ← A + r Op Code Operands A, r Description The contents of register r are added to the contents of the Accumulator, and the result is stored in the Accumulator. The r symbol identifies the registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register M Cycles...
  • Page 160 Z80 CPU User Manual P/V is set if overflow; otherwise, it is reset. N is reset. C is set if carry from bit 7; otherwise, it is reset. Example If the Accumulator contains and Register C contains , then upon the execution of an ADD A, C instruction, the Accumulator contains Z80 Instruction Set UM008011-0816...

  • Page 161: Add A, N

    Z80 CPU User Manual ADD A, n Operation A ← A + n Op Code Operands A, n Description The n integer is added to the contents of the Accumulator, and the results are stored in the Accumulator. M Cycles T States 4 MHz E.T.

  • Page 162: Add A, (Hl)

    Z80 CPU User Manual ADD A, (HL) Operation A ← A + (HL) Op Code Operands A, (HL) Description The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator, and the result is stored in the Accumulator. M Cycles T States 4 MHz E.T.

  • Page 163: Add A, (Ix + D)

    Z80 CPU User Manual ADD A, (IX + d) Operation A ← A + (IX+d) Op Code Operands A, (IX + d) Description The contents of the Index (register pair IX) Register is added to a two’s complement dis- placement d to point to an address in memory. The contents of this address is then added to the contents of the Accumulator and the result is stored in the Accumulator.

  • Page 164: Add A, (Iy + D)

    Z80 CPU User Manual ADD A, (IY + d) Operation A ← A + (IY+d) Op Code Operands A, (IY + d) Description The contents of the Index (register pair IY) Register is added to a two’s complement dis- placement d to point to an address in memory. The contents of this address is then added to the contents of the Accumulator, and the result is stored in the Accumulator.

  • Page 165: Adc A, S

    Z80 CPU User Manual ADC A, s Operation A ← A + s + CY Op Code Operands A, s This s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD instruction. These possible op code/operand combinations are assembled as follows in the object code: ADC A,r ADC A,n...
  • Page 166 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A, assembled as follows in the object code field: Register Description The s operand, along with the Carry Flag (C in the F Register) is added to the contents of the Accumulator, and the result is stored in the Accumulator.

  • Page 167: Sub S

    Z80 CPU User Manual SUB s Operation A ← A – s Op Code Operand This s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD instruction. These possible op code/operand combinations are assembled as follows in the object code: SUB r SUB n...
  • Page 168 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description The s operand is subtracted from the contents of the Accumulator, and the result is stored in the Accumulator.

  • Page 169: Sbc A, S

    Z80 CPU User Manual SBC A, s Operation A ← A – s – CY Op Code Operands A, s The s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD instructions. These possible op code/operand combinations are assembled as follows in the object code.
  • Page 170 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description The s operand, along with the Carry flag (C in the F Register) is subtracted from the con- tents of the Accumulator, and the result is stored in the Accumulator.

  • Page 171: And S

    Z80 CPU User Manual AND s Operation A ← A ˄ s Op Code Operand The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible op code/operand combinations are assembled as follows in the object code: AND r* AND n...
  • Page 172 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as follows: Register Description A logical AND operation is performed between the byte specified by the s operand and the byte contained in the Accumulator;...

  • Page 173: Or S

    Z80 CPU User Manual OR s Operation A ← A ˅ s Op Code Operand The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible op code/operand combinations are assembled as follows in the object code: OR r* OR n...
  • Page 174 Z80 CPU User Manual r identifies registers B, C–, D, E, H, L, or A specified in the assembled object code field, as follows: Register Description A logical OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator;...

  • Page 175: Xor S

    Z80 CPU User Manual XOR s Operation A ← A ⊕ s Op Code Operand The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations are assembled as follows in the object code: XOR r* XOR n...
  • Page 176 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as follows: Register Description The logical exclusive-OR operation is performed between the byte specified by the s oper- and and the byte contained in the Accumulator;...

  • Page 177: Cp S

    Z80 CPU User Manual CP s Operation A – s Op Code Operand The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible op code/operand combinations are assembled as follows in the object code: CP r* CP n...
  • Page 178 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as follows: Register Description The contents of the s operand are compared with the contents of the Accumulator. If there is a true compare, the Z flag is set.

  • Page 179: Inc R

    Z80 CPU User Manual INC r Operation r ← r + 1 Op Code Operand Description Register r is incremented and register r identifies any of the registers A, B, C, D, E, H, or L, assembled as follows in the object code. Register M Cycles T States...
  • Page 180 Z80 CPU User Manual N is reset. C is not affected. Example If the D Register contains , then upon the execution of an INC D instruction, the D Register contains Z80 Instruction Set UM008011-0816...

  • Page 181: Inc (Hl)

    Z80 CPU User Manual INC (HL) Operation (HL) ← (HL) + 1 Op Code Operand (HL) Description The byte contained in the address specified by the contents of the HL register pair is incre- mented. M Cycles T States 4 MHz E.T. 11 (4, 4, 3) 2.75 Condition Bits Affected...

  • Page 182: Inc (Ix+D)

    Z80 CPU User Manual INC (IX+d) Operation (IX+d) ← (IX+d) + 1 Op Code Operands (IX+d) Description The contents of Index Register IX (register pair IX) are added to the two’s-complement displacement integer, d, to point to an address in memory. The contents of this address are then incremented.

  • Page 183: Inc (Iy+D)

    Z80 CPU User Manual INC (IY+d) Operation (lY+d) ← (lY+d) + 1 Op Code Operands (lY+d) Description The contents of Index Register IY (register pair IY) are added to the two’s-complement displacement integer, d, to point to an address in memory. The contents of this address are then incremented.

  • Page 184: Dec M

    Z80 CPU User Manual DEC m Operation m ← m – 1 Op Code Operand The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous INC instructions. These possible op code/operand combinations are assembled as follows in the object code: DEC r* DEC (HL)
  • Page 185 Z80 CPU User Manual Description The byte specified by the m operand is decremented. Instruction M Cycles T States 4 MHz E.T. DEC r 1.00 DEC (HL) 11 (4, 4, 3) 2.75 DEC (IX+d) 23 (4, 4, 3, 5, 4, 3) 5.75 DEC (lY+d) 23 (4, 4, 3, 5, 4, 3)
  • Page 186 Z80 CPU User Manual General-Purpose Arithmetic and CPU Control Groups The following general-purpose arithmetic and CPU control group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. – see page 173 –...

  • Page 187: Daa

    Z80 CPU User Manual Operation Op Code Operands None. Description This instruction conditionally adjusts the Accumulator for BCD addition and subtraction operations. For addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC, NEG), the following table indicates the operation being performed: Hex Value Hex Value In Upper...
  • Page 188 Z80 CPU User Manual M Cycles T States 4 MHz E.T. 1.00 Condition Bits Affected S is set if most-significant bit of the Accumulator is 1 after an operation; otherwise, it is reset. Z is set if the Accumulator is 0 after an operation; otherwise, it is reset. H: see the DAA instruction table on the previous page.

  • Page 189: Cpl

    Z80 CPU User Manual Operation A ← A Op Code Operands None. Description The contents of the Accumulator (Register A) are inverted (one’s complement). M Cycles T States 4 MHz E.T. 1.00 Condition Bits Affected S is not affected. Z is not affected. H is set.

  • Page 190: Neg

    Z80 CPU User Manual Operation A ← 0 – A Op Code Operands None. Description The contents of the Accumulator are negated (two’s complement). This method is the same as subtracting the contents of the Accumulator from zero. address remains unchanged. Note: M Cycles T States...
  • Page 191 Z80 CPU User Manual Example The Accumulator contains the following data: Upon the execution of a NEG instruction, the Accumulator contains: UM008011-0816 Z80 Instruction Description...

  • Page 192: Ccf

    Z80 CPU User Manual Operation CY ← CY Op Code Operands None. Description The Carry flag in the F Register is inverted. M Cycles T States 4 MHz E.T. 1.00 Condition Bits Affected S is not affected. Z is not affected. H, previous carry is copied.

  • Page 193: Scf

    Z80 CPU User Manual Operation CY ← 1 Op Code Operands None. Description The Carry flag in the F Register is set. M Cycles T States 4 MHz E.T. 1.00 Condition Bits Affected S is not affected. Z is not affected. H is reset.

  • Page 194: Nop

    Z80 CPU User Manual Operation — Op Code Operands None. Description The CPU performs no operation during this machine cycle. M Cycles T States 4 MHz E.T. 1.00 Condition Bits Affected None. Z80 Instruction Set UM008011-0816...

  • Page 195: Halt

    Z80 CPU User Manual HALT Operation — Op Code HALT Operands None. Description The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received. While in the HALT state, the processor executes NOPs to maintain memory refresh logic. M Cycles T States 4 MHz E.T.
  • Page 196 Z80 CPU User Manual Operation IFF ← 0 Op Code Operands None. Description DI disables the maskable interrupt by resetting the interrupt enable flip-flops (IFF1 and IFF2). This instruction disables the maskable interrupt during its execution. Note: M Cycles T States 4 MHz E.T.
  • Page 197 Z80 CPU User Manual Operation IFF ← 1 Op Code Operands None. Description The enable interrupt instruction sets both interrupt enable flip flops (IFFI and IFF2) to a logic 1, allowing recognition of any maskable interrupt. During the execution of this instruction and the following instruction, maskable interrupts Note: are disabled.
  • Page 198 Z80 CPU User Manual IM 0 Operation Set Interrupt Mode 0 Op Code Operand Description The IM 0 instruction sets Interrupt Mode 0. In this mode, the interrupting device can insert any instruction on the data bus for execution by the CPU. The first byte of a multi-byte instruction is read during the interrupt acknowledge cycle.
  • Page 199 Z80 CPU User Manual IM 1 Operation Set Interrupt Mode 1 Op Code Operand Description The IM 1 instruction sets Interrupt Mode 1. In this mode, the processor responds to an interrupt by executing a restart at address 0038h M Cycles T States 4 MHz E.T.
  • Page 200 Z80 CPU User Manual IM 2 Operation Set Interrupt Mode 2 Op Code Operand Description The IM 2 instruction sets the vectored Interrupt Mode 2. This mode allows an indirect call to any memory location by an 8-bit vector supplied from the peripheral device. This vector then becomes the least-significant eight bits of the indirect pointer, while the I Register in the CPU provides the most-significant eight bits.
  • Page 201 Z80 CPU User Manual 16-Bit Arithmetic Group The following 16-bit arithmetic group instructions are each described in this section. Sim- ply click to jump to an instruction’s description to learn more. ADD HL, ss – see page 188 ADC HL, ss –...

  • Page 202: Add Hl, Ss

    Z80 CPU User Manual ADD HL, ss Operation HL ← HL + ss Op Code Operands HL, ss Description The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added to the contents of register pair HL and the result is stored in HL. In the assembled object code, operand ss is specified as follows: Register Pair...
  • Page 203 Z80 CPU User Manual C is set if carry from bit 15; otherwise, it is reset. Example If register pair HL contains the integer and register pair DE contains , then 4242h 1111h upon the execution of an ADD HL, DE instruction, the HL register pair contains 5353h UM008011-0816 Z80 Instruction Description...

  • Page 204: Adc Hl, Ss

    Z80 CPU User Manual ADC HL, ss Operation HL ← HL + ss + CY Op Code Operands HL, ss Description The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added with the Carry flag (C flag in the F Register) to the contents of register pair HL, and the result is stored in HL.
  • Page 205 Z80 CPU User Manual N is reset. C is set if carry from bit 15; otherwise, it is reset. Example If register pair BC contains , register pair HL contains , and the Carry Flag is 2222h 5437h set, then upon the execution of an ADC HL, BC instruction, HL contains 765Ah UM008011-0816 Z80 Instruction Description...

  • Page 206: Sbc Hl, Ss

    Z80 CPU User Manual SBC HL, ss Operation HL ← HL – ss – CY Op Code Operands HL, ss Description The contents of the register pair ss (any of register pairs BC, DE, HL, or SP) and the Carry Flag (C flag in the F Register) are subtracted from the contents of register pair HL, and the result is stored in HL.
  • Page 207 Z80 CPU User Manual N is set. C is set if borrow; otherwise, it is reset. Example If the HL register pair contains , register pair DE contains , and the Carry 9999h 1111h flag is set, then upon the execution of a SBC HL, DE instruction, HL contains 8887h UM008011-0816...

  • Page 208: Add Ix, Pp

    Z80 CPU User Manual ADD IX, pp Operation IX ← IX + pp Op Code Operands IX, pp Description The contents of register pair pp (any of register pairs BC, DE, IX, or SP) are added to the contents of Index Register IX, and the results are stored in IX. In the assembled object code, operand pp is specified as follows: Register Pair...
  • Page 209 Z80 CPU User Manual N is reset. C is set if carry from bit 15; otherwise, it is reset. Example If Index Register IX contains and register pair BC contains , then upon the 333h 5555h execution of an ADD IX, BC instruction, IX contains 8888h UM008011-0816 Z80 Instruction Description...

  • Page 210: Add Iy, Rr

    Z80 CPU User Manual ADD IY, rr Operation IY ← IY + rr Op Code Operands IY, rr Description The contents of register pair rr (any of register pairs BC, DE, IY, or SP) are added to the contents of Index Register IY, and the result is stored in IY. In the assembled object code, the rr operand is specified as follows: Register Pair...
  • Page 211 Z80 CPU User Manual N is reset. C is set if carry from bit 15; otherwise, it is reset. Example If Index Register IY contains and register pair BC contains , then upon the exe- 333h 555h cution of an ADD IY, BC instruction, IY contains 8888h UM008011-0816 Z80 Instruction Description...

  • Page 212: Inc Ss

    Z80 CPU User Manual INC ss Operation ss ← ss + 1 Op Code Operand Description The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are incremented. In the assembled object code, operand ss is specified as follows: Register Pair M Cycles...

  • Page 213: Inc Ix

    Z80 CPU User Manual INC IX Operation IX ← IX + 1 Op Code Operand Description The contents of Index Register IX are incremented. M Cycles T States 4 MHz E.T. 10 (4, 6) 2.50 Condition Bits Affected None. Example If Index Register IX contains the integer , then upon the execution of an INC IX 3300h...

  • Page 214: Inc Iy

    Z80 CPU User Manual INC IY Operation IY ← IY + 1 Op Code Operand Description The contents of Index Register IY are incremented. M Cycles T States 4 MHz E.T. 10 (4, 6) 2.50 Condition Bits Affected None. Example If the index register contains , then upon the execution of an INC IY instruction, 2977h...

  • Page 215: Dec Ss

    Z80 CPU User Manual DEC ss Operation ss ← ss – 1 Op Code Operand Description The contents of register pair ss (any of the register pairs BC, DE, HL, or SP) are decre- mented. In the assembled object code, operand ss is specified as follows: Register Pair M Cycles...

  • Page 216: Dec Ix

    Z80 CPU User Manual DEC IX Operation IX ← IX – 1 Op Code Operand Description The contents of Index Register IX are decremented. M Cycles T States 4 MHz E.T. 10 (4, 6) 2.50 Condition Bits Affected None. Example If Index Register IX contains , then upon the execution of a DEC IX instruction, 2006h...

  • Page 217: Dec Iy

    Z80 CPU User Manual DEC IY Operation IY ← IY– 1 Op Code Operand Description The contents of Index Register IY are decremented. M Cycles T States 4 MHz E.T. 10 (4, 6) 2.50 Condition Bits Affected None. Example If Index Register IY contains , then upon the execution of a DEC IY instruction, 7649h Index Register IY contains...
  • Page 218 Z80 CPU User Manual Rotate and Shift Group The following rotate and shift group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. RLCA – see page 205 – see page 207 RRCA –...

  • Page 219: Rlca

    Z80 CPU User Manual RLCA Operation Op Code RLCA Operands None. Description The contents of the Accumulator (Register A) are rotated left 1 bit position. The sign bit (bit 7) is copied to the Carry flag and also to bit 0. Bit 0 is the least-significant bit. M Cycles T States 4 MHz E.T.
  • Page 220 Z80 CPU User Manual Example The Accumulator contains the following data: Upon the execution of an RLCA instruction, the Accumulator and Carry flag contains: Z80 Instruction Set UM008011-0816...

  • Page 221: Rla

    Z80 CPU User Manual Operation Op Code Operands None. Description The contents of the Accumulator (Register A) are rotated left 1 bit position through the Carry flag. The previous contents of the Carry flag are copied to bit 0. Bit 0 is the least- significant bit.
  • Page 222 Z80 CPU User Manual Example The Accumulator and the Carry flag contains the following data: Upon the execution of an RLA instruction, the Accumulator and the Carry flag contains: Z80 Instruction Set UM008011-0816...

  • Page 223: Rrca

    Z80 CPU User Manual RRCA Operation Op Code RRCA Operands None. Description The contents of the Accumulator (Register A) are rotated right 1 bit position. Bit 0 is cop- ied to the Carry flag and also to bit 7. Bit 0 is the least-significant bit. M Cycles T States 4 MHz E.T.
  • Page 224 Z80 CPU User Manual Upon the execution of an RRCA instruction, the Accumulator and the Carry flag now con- tain: Z80 Instruction Set UM008011-0816...

  • Page 225: Rra

    Z80 CPU User Manual Operation Op Code Operands None. Description The contents of the Accumulator (Register A) are rotated right 1 bit position through the Carry flag. The previous contents of the Carry flag are copied to bit 7. Bit 0 is the least- significant bit.
  • Page 226 Z80 CPU User Manual Example The Accumulator and the Carry Flag contain the following data: Upon the execution of an RRA instruction, the Accumulator and the Carry flag now con- tain: Z80 Instruction Set UM008011-0816...

  • Page 227: Rlc R

    Z80 CPU User Manual RLC r Operation Op Code Operand Description The contents of register r are rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit 0. In the assembled object code, operand r is specified as fol- lows: Register M Cycles...
  • Page 228 Z80 CPU User Manual Condition Bits Affected S is set if result is negative; otherwise, it is reset. Z is set if result is 0; otherwise, it is reset. H is reset. P/V is set if parity even; otherwise, it is reset. N is reset.

  • Page 229: Rlc (Hl)

    Z80 CPU User Manual RLC (HL) Operation (HL) Op Code Operand (HL) Description The contents of the memory address specified by the contents of register pair HL are rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit 0.
  • Page 230 Z80 CPU User Manual Example The HL register pair contains and the contents of memory location are: 2828h 2828h Upon the execution of an RLC(HL) instruction, memory location and the Carry 2828h flag now contain: Z80 Instruction Set UM008011-0816...

  • Page 231: Rlc (Ix+D)

    Z80 CPU User Manual RLC (IX+d) Operation (IX+d) Op Code Operand (IX+d) Description The contents of the memory address specified by the sum of the contents of Index Register IX and the two’s-complement displacement integer, d, are rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit 0.
  • Page 232 Z80 CPU User Manual C is data from bit 7 of source register. Example Index Register IX contains and memory location contains the following 1000h 1022h data. Upon the execution of an RLC (IX+ ) instruction, memory location and the 1002h Carry flag now contain: Z80 Instruction Set...

  • Page 233: Rlc (Iy+D)

    Z80 CPU User Manual RLC (IY+d) Operation (IY+d) Op Code Operand (lY+d) Description The contents of the memory address specified by the sum of the contents of Index Register IY and the two’s-complement displacement integer, d, are rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit 0.
  • Page 234 Z80 CPU User Manual C is data from bit 7 of source register. Example Index Register IY contains and memory location contain the following 1000h 1002h data: Upon the execution of an RLC (IY+ ) instruction, memory location and the 1002h Carry flag now contain: Z80 Instruction Set...

  • Page 235: Rl M

    Z80 CPU User Manual RL m Operation Op Code Operand The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. In the assembled object code, the possible op code/operand combinations are specified as follows: RL r* RL (HL) RL (IX+d)
  • Page 236 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description The contents of the m operand are rotated left 1 bit position. The contents of bit 7 are cop- ied to the Carry flag, and the previous contents of the Carry flag are copied to bit 0.
  • Page 237 Z80 CPU User Manual Upon the execution of an RL D instruction, the D Register and the Carry flag now contain: UM008011-0816 Z80 Instruction Description...

  • Page 238: Rrc M

    Z80 CPU User Manual RRC m Operation Op Code Operand The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. In the assembled object code, the possible op code/operand combinations are specified as follows: Z80 Instruction Set UM008011-0816...
  • Page 239 Z80 CPU User Manual RRC r* RRC (HL) RRC (IX+d) RRC (IY+d) r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description The contents of the m operand are rotated right 1 bit position. The contents of bit 0 are copied to the Carry flag and also to bit 7.
  • Page 240 Z80 CPU User Manual Instruction M Cycles T States 4 MHz E.T. RRC r 8 (4, 4) 2.00 RRC (HL) 15 (4, 4, 4, 3) 3.75 RRC (IX+d) 23 (4, 4, 3, 5, 4, 3) 5.75 RRC (lY+d) 23 (4, 4, 3, 5, 4, 3) 5.75 Condition Bits Affected S is set if result is negative;...

  • Page 241: Rr M

    Z80 CPU User Manual RR m Operation Op Code Operand The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. In the assembled object code, the possible op code/operand combinations are specified as follows: UM008011-0816 Z80 Instruction Description...
  • Page 242 Z80 CPU User Manual RR r* RR (HL) RR (IX+d) RR (IY+d) r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description The contents of operand m are rotated right 1 bit position through the Carry flag. The con- tents of bit 0 are copied to the Carry flag and the previous contents of the Carry flag are copied to bit 7.
  • Page 243 Z80 CPU User Manual Instruction M Cycles T States 4 MHz E.T. RR r 8 (4, 4) 2.00 RR (HL) 15 (4, 4, 4, 3) 3.75 RR (IX+d) 23 (4, 4, 3, 5, 4, 3) 5.75 RR (lY+d) 23 (4, 4, 3, 5, 4, 3) 5.75 Condition Bits Affected S is set if result is negative;...

  • Page 244: Sla M

    Z80 CPU User Manual SLA m Operation Op Code Operand The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. In the assembled object code, the possible op code/operand combinations are specified as follows: SLA r* SLA (HL) SLA (IX+d)
  • Page 245 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description An arithmetic shift left 1 bit position is performed on the contents of operand m. The con- tents of bit 7 are copied to the Carry flag.
  • Page 246 Z80 CPU User Manual Upon the execution of an SLA L instruction, Register L and the Carry flag now contain: Z80 Instruction Set UM008011-0816...

  • Page 247: Sra M

    Z80 CPU User Manual SRA m Operation Op Code Operand The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. In the assembled object code, the possible op code/operand combinations are specified as follows: SRA r* SRA (HL) SRA (IX+d)
  • Page 248 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field: Register Description An arithmetic shift right 1 bit position is performed on the contents of operand m. The contents of bit 0 are copied to the Carry flag and the previous contents of bit 7 remain unchanged.
  • Page 249 Z80 CPU User Manual Upon the execution of an SRA (IX+ ) instruction, memory location and the 1003h Carry flag now contain: UM008011-0816 Z80 Instruction Description...

  • Page 250: Srl M

    Z80 CPU User Manual SRL m Operation Op Code Operand The operand m is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. In the assembled object code, the possible op code/operand combinations are specified as follows: SRL r* SRL (HL) SRL (IX+d)
  • Page 251 Z80 CPU User Manual r identifies registers B, C, D, E, H, L, or A. Description The contents of operand m are shifted right 1 bit position. The contents of bit 0 are copied to the Carry flag, and bit 7 is reset. Bit 0 is the least-significant bit. Instruction M Cycles T States...

  • Page 252: Rld

    Z80 CPU User Manual Operation Op Code Operands Description The contents of the low-order four bits (bits 3, 2, 1, and 0) of the memory location (HL) are copied to the high-order four bits (7, 6, 5, and 4) of that same memory location; the previous contents of those high-order four bits are copied to the low-order four bits of the Accumulator (Register A);...
  • Page 253 Z80 CPU User Manual P/V is set if the parity of the Accumulator is even after an operation; otherwise, it is reset. N is reset. C is not affected. Example The HL register pair contains and the Accumulator and memory location 5000h 5000h contain the following data.

  • Page 254: Rrd

    Z80 CPU User Manual Operation (HL) Op Code Operands Description The contents of the low-order four bits (bits 3, 2, 1, and 0) of memory location (HL) are copied to the low-order four bits of the Accumulator (Register A). The previous contents of the low-order four bits of the Accumulator are copied to the high-order four bits (7, 6, 5, and 4) of location (HL);...
  • Page 255 Z80 CPU User Manual P/V is set if the parity of the Accumulator is even after an operation; otherwise, it is reset. N is reset. C is not affected. Example The HL register pair contains and the Accumulator and memory location 5000h 5000h contain the following data.
  • Page 256 Z80 CPU User Manual Bit Set, Reset, and Test Group The following bit set, reset, and test group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. BIT b, r – see page 243 BIT b, (HL) –...

  • Page 257: Bit B, R

    Z80 CPU User Manual BIT b, r Operation Z ← rb Op Code Operands b, r Description This instruction tests bit b in register r and sets the Z flag accordingly. In the assembled object code, operands b and r are specified as follows: Bit Tested Register M Cycles...
  • Page 258 Z80 CPU User Manual H is set. P/V is unknown. N is reset. C is not affected. Example If bit 2 in Register B contains 0, then upon the execution of a BIT 2, B instruction, the Z flag in the F Register contains 1, and bit 2 in Register B remains at 0. Bit 0 in Register B is the least-significant bit.

  • Page 259: Bit B, (Hl)

    Z80 CPU User Manual BIT b, (HL) Operation Z ← (HL)b Op Code Operands b, (HL) Description This instruction tests bit b in the memory location specified by the contents of the HL reg- ister pair and sets the Z flag accordingly. In the assembled object code, operand b is speci- fied as follows: Bit Tested M Cycles...
  • Page 260 Z80 CPU User Manual Z is set if specified bit is 0; otherwise, it is reset. H is set. P/V is unknown. H is reset. C is not affected. Example If the HL register pair contains , and bit 4 in the memory location contains 1, 4444h 444h...

  • Page 261: Bit B, (Ix+D)

    Z80 CPU User Manual BIT b, (IX+d) Operation Z ← (IX+d)b Op Code Operands b, (IX+d) Description This instruction tests bit b in the memory location specified by the contents of register pair IX combined with the two’s complement displacement d and sets the Z flag accordingly. In the assembled object code, operand b is specified as follows: Bit Tested M Cycles...
  • Page 262 Z80 CPU User Manual Condition Bits Affected S is unknown. Z is set if specified bit is 0; otherwise, it is reset. H is set. P/V is unknown. N is reset. C is not affected. Example If Index Register IX contains and bit 6 in memory location contains 1, then 2000h...

  • Page 263: Bit B, (Iy+D)

    Z80 CPU User Manual BIT b, (IY+d) Operation Z ← (IY+d)b Op Code Operands b, (lY+d) Description This instruction tests bit b in the memory location specified by the contents of register pair IY combined with the two’s complement displacement d and sets the Z flag accordingly. In the assembled object code, operand b is specified as follows.
  • Page 264 Z80 CPU User Manual Condition Bits Affected S is unknown. Z is set if specified bit is 0; otherwise, it is reset. H is set. P/V is unknown. H is reset. C is not affected. Example If Index Register contains and bit 6 in memory location contains a 1, then 2000h...

  • Page 265: Set B, R

    Z80 CPU User Manual SET b, r Operation rb ← 1 Op Code Operands b, r Description Bit b in register r (any of registers B, C, D, E, H, L, or A) is set. In the assembled object code, operands b and r are specified as follows: Register M Cycles T States...
  • Page 266 Z80 CPU User Manual Example Upon the execution of a SET 4, A instruction, bit 4 in Register A is set. Bit 0 is the least- significant bit. Z80 Instruction Set UM008011-0816...

  • Page 267: Set B, (Hl)

    Z80 CPU User Manual SET b, (HL) Operation (HL)b ← 1 Op Code Operands b, (HL) Description Bit b in the memory location addressed by the contents of register pair HL is set. In the assembled object code, operand b is specified as follows: Bit Tested M Cycles T States...
  • Page 268 Z80 CPU User Manual Example If the HL register pair contains , then upon the execution of a SET 4, (HL) instruc- 3000h tion, bit 4 in memory location is 1. Bit 0 in memory location is the least-sig- 3000h 3000h nificant bit.

  • Page 269: Set B, (Ix+D)

    Z80 CPU User Manual SET b, (IX+d) Operation (IX+d)b ← 1 Op Code Operands b, (IX+d) Description Bit b in the memory location addressed by the sum of the contents of the IX register pair and the two’s complement integer d is set. In the assembled object code, operand b is spec- ified as follows: Bit Tested M Cycles...
  • Page 270 Z80 CPU User Manual Condition Bits Affected None. Example If the index register contains , then upon the execution of a SET 0, (IX + 2000h instruction, bit 0 in memory location is 1. Bit 0 in memory location is the 2003h 2003h least-significant bit.

  • Page 271: Set B, (Iy+D)

    Z80 CPU User Manual SET b, (IY+d) Operation (IY + d) b ← 1 Op Code Operands b, (IY + d) Description Bit b in the memory location addressed by the sum of the contents of the IY register pair and the two’s complement displacement d is set.
  • Page 272 Z80 CPU User Manual Condition Bits Affected None. Example If Index Register IY contains , then upon the execution of a Set 0, (IY+ ) instruc- 2000h tion, bit 0 in memory location is 1. Bit 0 in memory location is the least-sig- 2003h 2003h...

  • Page 273: Res B, M

    Z80 CPU User Manual RES b, m Operation sb ← 0 Op Code Operands b, m The b operand represents any bit (7 through 0) of the contents of the m operand, (any of r, (HL), (IX+d), or (lY+d)) as defined for the analogous SET instructions. These possible op code/operand combinations are assembled as follows in the object code: RES b, rn RES b, (HL)
  • Page 274 Z80 CPU User Manual Register Description Bit b in operand m is reset. Instruction M Cycles T States 4 MHz E.T. RES r 8 (4, 4) 2.00 RES (HL) 15 (4, 4, 4, 3) 3.75 RES (IX+d) 23 (4, 4, 3, 5, 4, 3) 5.75 RES (lY+d) 23 (4, 4, 3, 5, 4, 3)
  • Page 275 Z80 CPU User Manual Jump Group The following jump group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. JP nn – see page 262 JP cc, nn – see page 263 JR e –...

  • Page 276: Jp Nn

    Z80 CPU User Manual JP nn Operation PC ← nn Op Code Operand The first operand in this assembled object code is the low-order byte of a two-byte address. Note: Description Operand nn is loaded to register pair Program Counter (PC). The next instruction is fetched from the location designated by the new contents of the PC.

  • Page 277: Jp Cc, Nn

    Z80 CPU User Manual JP cc, nn Operation IF cc true, PC ← nn Op Code Operands cc, nn The first n operand in this assembled object code is the low-order byte of a 2-byte memory address. Description If condition cc is true, the instruction loads operand nn to register pair Program Counter (PC), and the program continues with the instruction beginning at address nn.
  • Page 278 Z80 CPU User Manual M Cycles T States 4 MHz E.T. 10 (4, 3, 3) 2.50 Condition Bits Affected None. Example If the Carry flag (i.e., the C flag in F Register) is set and address contains , then 1520h upon the execution of a JP C, instruction, the Program Counter contains 1520h...

  • Page 279: Jr E

    Z80 CPU User Manual JR e Operation PC ← PC + e Op Code Operand e–2 Description This instruction provides for unconditional branching to other segments of a program. The value of displacement e is added to the Program Counter (PC) and the next instruction is fetched from the location designated by the new contents of the PC.
  • Page 280 Z80 CPU User Manual Location Instruction – – – ← PC after jump Z80 Instruction Set UM008011-0816...

  • Page 281: Jr C, E

    Z80 CPU User Manual JR C, e Operation If C = 0, continue If C = 1, PC ← PC+ e Op Code Operands C, e e–2 Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag.
  • Page 282 Z80 CPU User Manual Example The Carry flag is set and it is required to jump back four locations from 480. The assembly language statement is – JR C The resulting object code and final Program Counter value is shown in the following table: Location Instruction ←...

  • Page 283: Jr Nc, E

    Z80 CPU User Manual JR NC, e Operation If C = 1, continue If C = 0, PC ← PC + e Op Code Operands NC, e e–2 Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag.
  • Page 284 Z80 CPU User Manual Example The Carry Flag is reset and it is required to repeat the jump instruction. The assembly lan- guage statement is JR NC The resulting object code and Program Counter after the jump are: Location Instruction ←...

  • Page 285: Jr Z, E

    Z80 CPU User Manual JR Z, e Operation If Z = 0, continue If Z = 1, PC ← PC + e Op Code Operands Z, e e–2 Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag.
  • Page 286 Z80 CPU User Manual Example The Zero Flag is set and it is required to jump forward five locations from address 300. The following assembly language statement is used: JR Z ,$ + 5 The resulting object code and final Program Counter value are: Location Instruction –...

  • Page 287: Jr Nz, E

    Z80 CPU User Manual JR NZ, e Operation If Z = 1, continue If Z = 0, PC ← pc + e Op Code Operands NZ, e e–2 Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag.
  • Page 288 Z80 CPU User Manual Example The Zero Flag is reset and it is required to jump back four locations from 480. The assem- bly language statement is – JR NZ The resulting object code and final Program Counter value is: Location Instruction ←...

  • Page 289: Jp (Hl)

    Z80 CPU User Manual JP (HL) Operation PC ← HL Op Code Operand (HL) Description The Program Counter (PC) is loaded with the contents of the HL register pair. The next instruction is fetched from the location designated by the new contents of the PC. M Cycles T States 4 MHz E.T.

  • Page 290: Jp (Ix)

    Z80 CPU User Manual JP (IX) Operation pc ← IX Op Code Operand (IX) Description The Program Counter (PC) is loaded with the contents of the IX register pair. The next instruction is fetched from the location designated by the new contents of the PC. M Cycles T States 4 MHz E.T.

  • Page 291: Jp (Iy)

    Z80 CPU User Manual JP (IY) Operation PC ← IY Op Code Operand (IY) Description The Program Counter (PC) is loaded with the contents of the IY register pair. The next instruction is fetched from the location designated by the new contents of the PC. M Cycles T States 4 MHz E.T.

  • Page 292: Djnz, E

    Z80 CPU User Manual DJNZ, e Operation B ← B – 1 If B = 0, continue If B ≠ 0, PC ← PC + e Op Code DJNZ Operand e–2 Description This instruction is similar to the conditional jump instructions except that a register value is used to determine branching.
  • Page 293 Z80 CPU User Manual Condition Bits Affected None. Example A typical software routine is used to demonstrate the use of the DJNZ instruction. This routine moves a line from an input buffer (INBUF) to an output buffer (OUTBUF). It moves the bytes until it finds a CR, or until it has moved 80 bytes, whichever occurs first. 8, 80 ;Set up counter HL, Inbuf...
  • Page 294 Z80 CPU User Manual Call and Return Group The following call and return group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. CALL nn – see page 281 CALL cc, nn –...

  • Page 295: Call Nn

    Z80 CPU User Manual CALL nn Operation (SP – 1) ← PCH, (SP – 2) ← PCL, PC ← nn Op Code CALL Operand The first of the two n operands in the assembled object code above is the least-significant byte of a 2-byte memory address.
  • Page 296 Z80 CPU User Manual Example The Program Counter contains , the Stack Pointer contains , and memory 1A47h 3002h locations contain the following data. Location Contents 1A47h IA48h 1A49h If an instruction fetch sequence begins, the 3-byte instruction CD is fetched to the 3521h CPU for execution.

  • Page 297: Call Cc, Nn

    Z80 CPU User Manual CALL cc, nn Operation IF cc true: (sp – 1) ← PCH (sp – 2) ← PCL, pc ← nn Op Code CALL Operands cc, nn The first of the two n operands in the assembled object code above is the least-significant byte of the 2-byte memory address.
  • Page 298 Z80 CPU User Manual Relevant Condition Flag Non-Zero (NZ) Zero (Z) Non Carry (NC) Carry (C) Parity Odd (PO) Parity Even (PE) Sign Positive (P) Sign Negative (M) If cc is true: M Cycles T States 4 MHz E.T. 17 (4, 3, 4, 3, 3) 4.25 If cc is false: M Cycles...

  • Page 299: Ret

    Z80 CPU User Manual Operation pCL ← (sp), pCH ← (sp+1) Op Code Operands None. Description The byte at the memory location specified by the contents of the Stack Pointer (SP) Regis- ter pair is moved to the low-order eight bits of the Program Counter (PC). The SP is now incremented and the byte at the memory location specified by the new contents of this instruction is fetched from the memory location specified by the PC.

  • Page 300: Ret Cc

    Z80 CPU User Manual RET cc Operation If cc true: PCL ← (sp), pCH ← (sp+1) Op Code Operand Description If condition cc is true, the byte at the memory location specified by the contents of the Stack Pointer (SP) Register pair is moved to the low-order eight bits of the Program Coun- ter (PC).
  • Page 301 Z80 CPU User Manual If cc is true, then the following data is returned: M Cycles T States 4 MHz E.T. 11 (5, 3, 3) 2.75 If cc is false, then the following data is returned: M Cycles T States 4 MHz E.T.

  • Page 302: Reti

    Z80 CPU User Manual RETI Operation Return from Interrupt Op Code RETI Operands None. Description This instruction is used at the end of a maskable interrupt service routine to: Restore the contents of the Program Counter (analogous to the RET instruction) •...
  • Page 303 Z80 CPU User Manual B generates an interrupt and is acknowledged. The interrupt enable out, IEO, of B goes Low, blocking any lower priority devices from interrupting while B is being serviced. Then A generates an interrupt, suspending service of B. The IEO of A goes Low, indicat- ing that a higher priority device is being serviced.

  • Page 304: Retn

    Z80 CPU User Manual RETN Operation Return from nonmaskable interrupt Op Code RETN Operands None. Description This instruction is used at the end of a nonmaskable interrupts service routine to restore the contents of the Program Counter (analogous to the RET instruction). The state of IFF2 is copied back to IFF1 so that maskable interrupts are enabled immediately following the RETN if they were enabled before the nonmaskable interrupt.
  • Page 305 Z80 CPU User Manual That address begins an interrupt service routine that ends with a RETN instruction. Upon the execution of a RETN instruction, the contents of the former Program Counter are popped off the external memory stack, low-order first, resulting in stack pointer contents .

  • Page 306: Rst P

    Z80 CPU User Manual RST p Operation (SP – 1) ← PCH, (SP – 2) ← PCL, PCH ← 0, PCL ← P Op Code Operand Description The current Program Counter (PC) contents are pushed onto the external memory stack, and the Page 0 memory location assigned by operand p is loaded to the PC.
  • Page 307 Z80 CPU User Manual M Cycles T States 4 MHz E.T. 11 (5, 3, 3) 2.75 Example If the Program Counter contains , then upon the execution of an RST (object 15B3h code ) instruction, the PC contains as the address of the next fetched op 1101111 0018h code.
  • Page 308 Z80 CPU User Manual Input and Output Group The following input and output group instructions are each described in this section. Sim- ply click to jump to an instruction’s description to learn more. IN A, (n) – see page 295 IN r (C) –...

  • Page 309: In A, (N)

    Z80 CPU User Manual IN A, (n) Operation A ← (n) Op Code Operands A, (n) Description The operand n is placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of the Accumulator also appear on the top half (A8 through A15) of the address bus at this time.

  • Page 310: In R (C)

    Z80 CPU User Manual IN r (C) Operation r ← (C) Op Code Operands r, (C) Description The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8 through A15) of the address bus at this time.
  • Page 311 Z80 CPU User Manual Condition Bits Affected S is set if input data is negative; otherwise, it is reset. Z is set if input data is 0; otherwise, it is reset. H is reset. P/V is set if parity is even; otherwise, it is reset. N is reset.

  • Page 312: Ini

    Z80 CPU User Manual Operation (HL) ← (C), B ← B – 1, HL ← HL + 1 Op Code Operands None. Description The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports.
  • Page 313 Z80 CPU User Manual Example Register C contains , Register B contains , the HL register pair contains 1000h and byte is available at the peripheral device mapped to I/O port address . Upon the execution of an INI instruction, memory location contains , the HL register 1000h...

  • Page 314: Inir

    Z80 CPU User Manual INIR Operation (HL) ← (C), B ← B – 1, HL ← HL +1 Op Code INIR Operands None. Description The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports.
  • Page 315 Z80 CPU User Manual Condition Bits Affected S is unknown. Z is set. H is unknown. P/V is unknown. N is set. C is not affected. Example Register C contains , Register B contains , the HL register pair contains 1000h and the following sequence of bytes is available at the peripheral device mapped to I/O port of address...

  • Page 316: Ind

    Z80 CPU User Manual Operation (HL) ← (C), B ← B – 1, HL ← HL – 1 Op Code Operands None. Description The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports.
  • Page 317 Z80 CPU User Manual Example Register C contains , Register B contains , the HL register pair contains 1000h and byte is available at the peripheral device mapped to I/O port address . Upon the execution of an IND instruction, memory location contains , the HL regis- 1000h...

  • Page 318: Indr

    Z80 CPU User Manual INDR Operation (HL) ← (C), B ← 131, HL ← HL1 Op Code INDR Operands None. Description The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B is used as a byte coun- ter, and its contents are placed on the top half (A8 through A15) of the address bus at this time.
  • Page 319 Z80 CPU User Manual Condition Bits Affected S is unknown. Z is set. H is unknown. P/V is unknown. N is set. C is not affected. Example Register C contains , Register B contains , the HL register pair contains 1000h and the following sequence of bytes is available at the peripheral device mapped to I/O port address...

  • Page 320: Out (N), A

    Z80 CPU User Manual OUT (n), A Operation (n) ← A Op Code Operands (n), A Description The operand n is placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of the Accumulator (Register A) also appear on the top half (A8 through A15) of the address bus at this time.

  • Page 321: Out (C), R

    Z80 CPU User Manual OUT (C), r Operation (C) ← r Op Code Operands (C), r Description The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8 through A15) of the address bus at this time.
  • Page 322 Z80 CPU User Manual Condition Bits Affected None. Example If Register C contains and the D Register contains , then upon the execution of an OUT (C), D instruction, byte is written to the peripheral device mapped to I/O port address Z80 Instruction Set UM008011-0816...

  • Page 323: Outi

    Z80 CPU User Manual OUTI Operation (C) ← (HL), B ← B – 1, HL ← HL + 1 Op Code OUTI Operands None. Description The contents of the HL register pair are placed on the address bus to select a location in memory.
  • Page 324 Z80 CPU User Manual Example If Register C contains , Register B contains , the HL register pair contains 100014 and memory address contains , then upon the execution of an OUTI instruc- 1000h 5914 tion, Register B contains , the HL register pair contains , and byte is writ- 1001h...

  • Page 325: Otir

    Z80 CPU User Manual OTIR Operation (C) ← (HL), B ← B – 1, HL ← HL + 1 Op Code OTIR Operands None. Description The contents of the HL register pair are placed on the address bus to select a location in memory.
  • Page 326 Z80 CPU User Manual If B = 0: M Cycles T States 4 MHz E.T. 16 (4, 5, 3, 4) 4.00 Condition Bits Affected S is unknown. Z is set. H is unknown. P/V is unknown. N is set. C is not affected. Example Register C contains , Register B contains...

  • Page 327: Outd

    Z80 CPU User Manual OUTD Operation (C) ← (HL), B ← B – 1, HL ← HL – 1 Op Code OUTD Operands None. Description The contents of the HL register pair are placed on the address bus to select a location in memory.
  • Page 328 Z80 CPU User Manual Example If Register C contains , Register B contains , the HL register pair contains 1000h and memory location contains , then upon the execution of an OUTD instruc- 1000h tion, Register B contains , the HL register pair contains , and byte is writ- 0FFFh...

  • Page 329: Otdr

    Z80 CPU User Manual OTDR Operation (C) ← (HL), B ← B – 1, HL ← HL – 1 Op Code OTDR Operands None. Description The contents of the HL register pair are placed on the address bus to select a location in memory.
  • Page 330 Z80 CPU User Manual If B = 0: M Cycles T States 4 MHz E.T. 16 (4, 5, 3, 4) 4.00 Condition Bits Affected S is unknown. Z is set. H is unknown. P/V is unknown. N is set. C is not affected. Example Register C contains , Register B contains...

  • Page 331: Customer Support

    Z80 CPU User Manual Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other fac- ets about Zilog product offerings, please visit the Zilog Knowledge Base at http:// zilog.com/kb...
  • Page 332 Z80 CPU User Manual Customer Support UM008011-0816...

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