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MEVB SUPPORT INFORMATION
Table 4-5. Logic Analyzer Connector J11 Pin Assignments
Pin
1
2
3
4 – 19
20
Table 4-6. Logic Analyzer Connector J12 Pin Assignments
Pin
1, 2
3
4
5
6
7
4-4
Mnemonic
+5V
+5 VDC POWER – Input voltage (+5Vdc @ 1.0 A) used
by the MEVB logic circuits. (To make this pin a no
connection, remove the jumper from jumper header W9
on the MPFB.)
SPARE
No connection
DS
DATA STROBE – Active-low output signal. During a
read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
D15 – D0
DATA BUS 15 – 0 – 16 bits of the MCU bi-directional
data bus lines.
GND
GROUND
Mnemonic
SPARE
No connection
CLKOUT
SYSTEM CLOCK OUT – Output signal that is the MCU
internal system clock.
BERR
BUS ERROR – Active-low signal that indicates a
memory access error has occurred.
BKPT /
BREAKPOINT – Active-low input signal that signals a
hardware breakpoint to the CPU.
DSCLK
Development Serial Clock – Clock input signal for
background debug mode.
FREEZE
FREEZE – Output signal that indicates the CPU has
acknowledged a breakpoint.
QUOT
QUOTIENT OUT – Output signal that furnishes the
quotient bit of the polynomial divider for test purposes.
LAT-DSO
LATCHED INSTRUCTION PIPE 0 – Latched output
(Latched IPIPE0)
signal of the first state of IPIPE0 for CPU16-based
MCUs; indicates instruction pipeline activity.
Logic low for CPU32-based MCUs.
Signal
Signal
M68MPB333UM/D
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