Panasonic KX-TA1232 Service Manual page 46

OGM (Out Going Message) Memory Circuit
DTMF Repeat Circuit
End of Call Detection Circuit
Highway Control Circuit
Timing Signal Generator Circuit
CPU Circuit
Composition:
68C03 8 bit CPU (IC1)
ROM 256 kbite (IC2)
SRAM 8 kbit (IC3)
IC7, IC25, IC27, IC32, IC36, IC46
Circuit Operation:
This circuit is a circuit which controls the DISA CARD according to the program in the ROM (IC2)
by the CPU (IC1). It is connected with main CPU on CPU BOARD through the parallel FIFO Circuit,
and controls this card by following the commands from the main CPU.
Parallel FIFO Memory Circuit
Composition:
Gate Array (IC5)
IC6, IC37, IC38, IC39, IC40, IC41
Circuit Operation:
Parallel FIFO Memory Circuit is a circuit which functions the data communication interface
between the DISA-CPU and the main CPU on CPU BOARD. This circuit has each 16 bite buffer in
the up and down directions. This FIFO memory is functioned by Gate Array(IC5).
ADPCM CODEC Circuit
Composition:
ADPCM IC (IC53,IC54)
CODEC IC (IC57,IC58,IC61)
AGC Circuit (IC70,Q7,Q8, etc)
Path Selector (IC37,IC38,IC42,IC43)
Circuit Operation:
This circuit is a circuit which converts the ADPCM data of OGM (Out Going Message) stored in
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