Agilent Technologies 6023A Operating Manual page 94

*SRE
Meaning and Type
Service Request Enable
Description
This command sets the condition of the Service Request Enable Register. This register determines which events of the
Status Byte Register (see *STB for its bit configuration) are summed into the MSS (Master Status Summary) and RQS
(Request for Service) bits. RQS is the service request bit that is cleared by a serial poll; the MSS is not cleared when read.
A 1 in any Service Request Enable Register bit position enables the corresponding Status Byte bit to set the RQS and MSS
bits. All the enabled Service Request Enable Register bits then are logically ORed to cause Bit 6 of the Status Byte Register
to be set. See "Status Reporting" for more details concerning this process.
If *PSC is programmed to zero, *SRE causes a write cycle to nonvolatile memory. Non volatile memory has
a finite maximum number of write cycles. Programs that repeatedly cause write cycles to nonvolatile
memory can eventually exceed the maximum number of write cycles and cause the memory to fail.
Command Syntax
Parameters
Default Value
Example
Query Syntax
Returned Parameters
*STB?
Meaning and Type
Status Byte Device Status
Description
This query reads the Status Byte register without clearing it. The register is cleared only when subsequent action clears all
its set bits. See "Status Reporting" for more information about the Status Byte register.
A serial poll also returns the value of the Status Byte register, except that bit 6 returns RQS instead of MSS. A serial poll
clears RQS, but not MSS. When MSS is set, it indicates that the power supply has one or more reasons for requesting
service.
Bit Position 7
Condition OPER
Bit Weight 128
ESB = Event status byte summary; MAV = Message available; MSS = Master status summary; OPER = Operation status
summary; QUES = Questionable status summary
l
AIso represents RQS (Request for service).
Query Syntax
Returned Parameters
Standard Commands for Programmable Instruments (SCPI)
94
Device Interface
*SRE <NRf>
0 to 255
(See *PSC)
*SRE 20
*SRE?
<NR1> (Register binary value)
Bit Configuration of Status Byte Register
6 5
1
MSS ESB
64 32
2
These bits are always zero.
*STB?
(Register binary value)
<NR1>
4 3
MAV QUES
16 8
2 1
2
4 2
0
1