Denon RCD-N7 Service Manual page 95

6 OUT gate driver output
7 VCC IC supply voltage
8 GND Common ground
1.2 Package PG-DIP-8
ICE2QS01 (SMPS : IC93)
ZC 1
REG 2
CS 3
HV 4
2 Representative block diagram
Figure 1 Pin Configuration PG-DIP-8(top view)
ICE2QS01 Block Diagram
1.3 Pin Functionality
ZC (Zero Crossing)
ZC
At this pin, the voltage from the auxiliary winding after
1
a time delay circuit is applied. Internally, this pin is
connected to the zero-crossing detector for switch-on
determination. Additionally, the output overvoltage
detection is realized by comparing the voltage V
an internal preset threshold.
REG
2
Version 2.0
R
Reg
V REF
CS
3
power management
HV
4, 5
VCC
7
Figure 2 Representative Blockdigram
CS (Current Sensing)
This pin is connected to the shunt resistor for the
primary current sensing, externally, and the PWM
signal generator for switch-off determination (together
with the regulation voltage), internally. Moreover, short-
winding protection is realised by monitoring the voltage
V during on-time of the main power switch.
cs
8 GND
HV (High Voltage)
The pin HV is connected to the bus voltage, externally,
and to the power cell, internally. The current through
this pin pre-charges the VCC capacitor once the supply
7 VCC
bus voltage is applied. Additionally, the current through
this pin supplies the IC in case that the output voltage
is lowered during active burst mode operation, or
during latch-off mode.
6 OUT
OUT (Gate drive output)
This output signal drives the external main power
5 HV
switch, which is a power MOSFET in most case.
VCC (Power supply)
This is the IC power supply pin. Externally, this pin is
connected to the VCC capacitor, which is supplied by
the inside power cell during VCC charge-up, burst
mode operation at lowered output voltage or during
latched-off of the IC, and the auxiliary winding during
V
ZCT2
normal operation or burst mode operation with high
enough voltage across the auxiliary winding. Based on
this voltage, the VCC under- or over-voltage protection
V
ZCT1
are implemented.
GND (Ground)
V
OLP
OLP
This is the common ground of the controller.
with
V zc
VCC
VCCOVP
OVP
VCC
UVP
5
V
vccuvp
output
V
OPOVP
OVP
V
csSW
SWP
power cell
controller
1 Pin Configuration and Functionalit
1.1 Pin Configuration
Pin Symbol
1 ZC
2 REG
3 Quasi-Resonant PWM Controller CS
4, 5 HV
6 OUT
Representative block diagram
7 VCC
8 GND
1.2 Package PG-DIP-8
ringing
ZC 1
suppression
time control
Zero-crossing
REG 2
counter
up/down
counter
CS 3
auto
restart
active burst
control
HV 4
December 2006
Figure 1 Pin Configuration PG-DIP-8(top view)
latch
off
1.3 Pin Functionality
current limitation /
foldback correction
ZC (Zero Crossing)
Vcsth
At this pin, the voltage from the auxiliary winding after
a time delay circuit is applied. Internally, this pin is
connected to the zero-crossing detector for switch-on
determination. Additionally, the output overvoltage
current measurement
detection is realized by comparing the voltage V
an internal preset threshold.
V
os
Version 2.0
95
Function
Zero Crossing
Regulation
Primary Current Sensing
High Voltage input
ICE2QS01
gate driver output
IC supply voltage
Common ground
8
7
6
5
on/off FF
gate driver
v1
Pin Conf
REG (Regulation
Normally, an exte
for a smooth v
connected to the
determination (t
signal), the digita
reduction with
operation, and th
burst mode ope
control during bu
open-loop / ove
monitoring the vo
CS (Current Sens
This pin is conn
primary current
signal generator
with the regulatio
winding protectio
V during on-tim
cs
GND
HV (High Voltage
The pin HV is con
and to the powe
this pin pre-charg
VCC
bus voltage is app
this pin supplies
is lowered durin
during latch-off m
OUT
OUT (Gate drive
This output sign
HV
switch, which is a
VCC (Power sup
This is the IC po
connected to the
the inside powe
mode operation
latched-off of the
normal operation
enough voltage a
this voltage, the V
OUT
are implemented
6
GND (Ground)
This is the comm
with
zc
GND
8
5