Denon RCD-N7 Service Manual page 90

TAS5508 (MAIN : IC51)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VRA_PLL
1
PLL_FLT_RET
2
PLL_FLTM 3
PLL_FLTP
4
AVSS
5
AVSS
6
VRD_PLL
7
AVSS_PLL
8
AVDD_PLL 9
VBGAP 10
RESET
11
HP_SEL
12
PDN
13
MUTE
14
DVDD 15
DVSS 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TAS5508
8-Channel Digital Audio PWM Processor
SLES091C – FEBRUARY 2004 – REVISED AUGUST 2005
2.1.3 Terminal Descriptions
TAS5508 Pin Discriptions
T TERMINAL
A
NAME
0°C to 70°C
AVDD_PLL
AVSS
AVSS_PLL
BKND_ERR
DVDD
DVDD_PWM
DVSS
DVSS_PWM
HP_SEL
LRCLK
MCLK
MUTE
OSC_CAP
PDN
PLL_FLT_RET
PLL_FLTM
PLL_FLTP
PSVC
PWM_HPML
PWM_HPMR
PWM_HPPL
PWM_HPPR
PWM_M_1
PWM_M_2
PWM_M_3
PWM_M_4
PWM_M_5
PWM_M_6
PWM_M_7
PWM_M_8
PWM_P_1
PWM_P_2
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups => logic-1 input; pulldowns => logic-0 input). Devices that drive
inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 200 mA, while maintaining a logic-1 drive level.
18 Description
PAG PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PLASTIC 64-PIN PQFP (PN)
5-V
TYPE (1) TERMINATION
TOLERANT
NO.
TAS5508PAG
9 P
5, 6 P
8 P
37 DI Pullup
15, 36 P
54 P
16, 34, P
35, 38
53 P
12 DI 5 V Pullup
26 DI 5 V
63 DI 5 V Pulldown
14 DI 5 V Pullup
18 AO
13 DI 5 V Pullup
2 AO
3 AO
4 AI
32 O
59 DO
61 DO
60 DO
62 DO
40 DO
42 DO
44 DO
46 DO
55 DO
57 DO
49 DO
51 DO
41 DO
43 DO
VR_PWM
PWM_P_4
PWM_M_4
PWM_P_3
PWM_M_3
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VALID
DVSS
BKND_ERR
DVDD
DVSS
DVSS
VR_DIG
P0010-01
(2) DESCRIPTION
3.3-V analog power supply for PLL. This terminal can be connected to the same
power source used to drive power terminal DVDD, but to achieve low PLL jitter,
this terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR
capacitor.
Analog ground
Analog ground for PLL. This terminal should reference the same ground as
terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must
be minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground-distribution techniques to achieve a quiet ground reference
at this terminal.
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to any system parameters, with
all H-bridge drive signals going to a hard-mute (M) state.
3.3-V digital power supply
3.3-V digital power supply for PWM
Digital ground
Description
17
Digital ground for PWM
Headphone in/out selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
Serial-audio data left/right clock (sampling-rate clock)
MCLK is a 3.3-V master clock input. The input frequency of this clock can range
from 4 MHz to 50 MHz.
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
Oscillator capacitor
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The internal parameters are preserved through
a power-down cycle, as long as RESET is not active. The duration for system
recovery from power down is 100 ms.
PLL external filter return
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL positive input. Connected to PLL_FLT_RTN via an RC network
Power-supply volume control PWM output
PWM left-channel headphone (differential –)
PWM right-channel headphone (differential –)
PWM left-channel headphone (differential +)
PWM right-channel headphone (differential +)
PWM 1 output (differential –)
PWM 2 output (differential –)
PWM 3 output (differential –)
PWM 4 output (differential –)
PWM 5 output (differential –)
PWM 6 output (differential –)
PWM 7 (lineout L) output (differential –)
PWM 8 (lineout R) output (differential –)
PWM 1 output (differential +)
PWM 2 output (differential +)
90
www.ti.com