I/O Address Map - ICS Advent PB751-AT Product Manual

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PB751-AT MANUAL
-MEM CS16
I
-MEMR
O
-MEMW
O
OSC
O
-REFRESH
O
RESET DRV
O
SA0-19
(A0-19)
SBHE
O
SD0-15
I/O
-SMEMR
O
-SMEMW
O
T/C
O

I/O ADDRESS MAP

The PB751-AT card address can be selected anywhere within the I/O address range 000-3FF
hex or the Memory address range 00000-FF000 providing that the address does not over lap
that of other installed functions. It is intended that I/O base addresses be selected at four-byte
intervals and that memory base address be selected at 4096 byte intervals.
Table 1 lists standard I/O address assignments.
Page 6
to gain control of the address, data, and control lines of the bus.
The controlling processor may need to assume responsibility to
refresh system memory every 15 usec.
Memory 16-Bit Chip Select signals a 16-bit, one-wait-state
memory cycle. This signal is active low and should be driven
with an open collector or tri state driver capable of sinking 20 mA.
Memory Read (AT). This signal tells bus memory devices to put
data onto the data bus. See -SMEMR to follow.
Memory Write (AT). This signal tells bus memory devices to put
the data onto the data bus. See -SMEMW to follow.
A 50% duty cycle clock signal with a frequency of 14.31818 MHz
This line is used in the AT to signal a memory refresh cycle. -
DACK0 is used for this purpose in the PC/XT. Active low.
Used to reset or initialize system logic on power-up or during low
line voltage. Synchronized to the falling edge of CLK.
O
Address lines for the first 1 MB of memory. SA0 is the
least significant bit (LSB).
Bus High Enable (system) indicates a 16 bit transfer of data.
Data bits. SD0 is the least significant bit (LSB).
Memory Read. This command tells memory on the bus to drive
its data onto the data bus. Used only with the lower 1 MB of
memory. Active low.
Memory Write. This command instructs memory devices on the
bus to store the data present on the data bus. Used only on the
lower 1 MB of memory. Active low.
Terminal Count. This signal provides a pulse when the terminal
count for a DMA cycle is reached.
FUNCTIONAL DESCRIPTION
MANUAL 00650-100-10

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