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PB751-AT MANUAL
BALE
(ALE)
O
CLK
O
-DACK1-7
(-DACK0-3)
O
DRQ0-7
(DRQ1-3)
O
-I/O CH CHK I
I/O
I/O CH RDY
I
-I/O CS16
I
-IOR
O
-IOW
O
IRQ2-7, IRQ9-12,
& IRQ14-15
I
LA17-23
I/O
-MASTER
I
MANUAL 00650-100-10
Address Latch Enable. This line is used to latch valid addresses
and memory decodes from the microprocessor. It's available to
the I/O channel as an indicator of a valid microprocessor or DMA
address (when used with AEN). Microprocessor addresses SA0
through SA19 are latched with the falling edge of BALE. BALE is
forced high during DMA cycles.
System Clock. This clock signal may vary from 6 MHz to 8.33
MHz or higher.
DMA acknowledge lines used to acknowledge DMA requests
(DRQ). Active low.
DMA Request lines from devices on the bus that need DMA
service.
The line must be held high until the corresponding
DACK line goes active (low). These lines are prioritized. DRQ0
has highest priority and DRQ7 has lowest priority.
through DRQ3 perform 8-bit transfers and DRQ5 through DRQ7
perform 16 bit transfers.
channel.
Channel Check. When low, a device on the bus has detected a
parity error.
I/O Channel Ready. Pulled low (not ready) by a memory or I/O
device on the bus that needs more time. Never hold low for more
than 10 clock cycles (XT) or 2.5 usec (AT). Cycles are extended in
integral multiples of CLK cycles.
I/O 16-bit Chip Select. Signals a 16-bit one-wait-state I/O cycle.
This signal is active low and should be driven with an open
collector or tri-state driver capable of sinking 20 mA.
I/O Read command. This line tells an I/O device on the bus to
drive its data onto the data bus. Active low.
I/O Write command. This line instructs an I/O device on the bus
to read the data present on the data lines.
Interrupt Request lines used by peripherals when they need
attention. Interrupt requests are prioritized with IRQ9 through
IRQ12 and IRQ14 through IRQ15 having the highest priority
(IRQ9 is the highest) and IRQ2 through IRQ7 having the lowest
priority (IRQ7 is the lowest). An interrupt line must be held high
until the microprocessor acknowledges the interrupt request
(Interrupt Service routine).
Interrupt 8 is used for the real time clock. Interrupt 13 is not
available on the I/O channel.
Unlatched address lines valid when BALE is high. I/O devices
should latch these signals when BALE falls. Used for one wait-
state memory cycles.
A processor on the I/O channel may use this signal with a DRQ
FUNCTIONAL DESCRIPTION
DRQ4 is not available on the I/O
DRQ0
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