36-Pin Connector; Bus Signal List - ICS Advent PB751-AT Product Manual

PB751-AT MANUAL

36-PIN CONNECTOR

-MEM CS16 >
-I/O CS16 >
S IRQ10 >
O IRQ11 >
L IRQ12 >
D IRQ15 >
E IRQ14 >
R -DACK0 <
DRQ0 >
S -DACK5 <
I DRQ5 >
D -DACK6 <
E DRQ6 >
-DACK7 <
DRQ7 >
+5VDC
-MASTER
Ground
NOTES
1. > : Symbols pointing toward the connector designate signals into the card from devices
on the bus.
2. < : Symbols pointing away from the connector designate signals from the card to
devices on the bus.
3. <>: Double symbols indicate bi-directional signals.
4. A "minus" sign before the signal name signifies active low.
5. In the PC and PC/XT, the bus consists only of the 62-pin portion. Some of the signal
names are different but the functionality remains the same.

BUS SIGNAL LIST

The signal names used in this listing are for the AT Bus. When appropriate, the older names
used for the PC/XT are included in parenthesis. "I" indicates that the signal is an input from
the bus to the card and "O" signifies an output from the card to the bus. See the AT technical
manual for a more detailed description of these signals.
SIGNAL I/O
-OWS I
(or -ENDXFR)
AEN O
Page 4
End Nearest to 62-Pin Connector
D1 C1 > SBHE
D2 C2 <> LA23
D3 C3 <> LA22
D4 C4 <> LA21
D5 C5 <> LA20
D6 C6 <> LA19
D7 C7 <> LA18
D8 C8 <> LA17
D9 C9 > -MEMR
D10 C10 > -MEMW
D11 C11 <> SD08
D12 C12 <> SD09
D13 C13 <> SD10
D14 C14 <> SD11
D15 C15 <> SD12
D16 C16 <> SD13
D17 C17 <> SD14
D18 C18 <> SD15
DESCRIPTION
Zero Wait State. Fast bus devices pull this line low to prevent the
CPU from inserting extra wait cycles. The OWS signal tells the
microprocessor that it can complete the present bus cycle without
inserting any additional wait cycles.
Address Enable. When this line is high, the DMA controller has
control of the address lines, data lines, memory read/write, and
I/O read/write.
FUNCTIONAL DESCRIPTION
C
O
M
P
O
N
E
N
T
S
I
D
E
MANUAL 00650-100-10