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3.3
Performance Characteristics
Processor Power–up Cycle
Part
Number
Blink
Brightness
Send Character
Clear
Cursor Locate
Home
Horizontal Scroll
Reset
Vertical Scroll
Brightness Control
Viewing Angle
Dedicated Interface Lines:
Industrial Electronic Engineers, Inc.
Van Nuys, California
04/10/02
4 X 20
2 X 20
036X2
036X2
–100
–105
300
170
305
170
315
170
2105
410
305
170
300
170
1830
635
850
815
2510
410
Execution Times (in
Software or Hardware. Varies display brightness level in 8 discrete steps.
The Hardware brightness level control sets the upper brightness level limit.
Software control cannot advance brightness level above the hardware set limit.
The displays are readable within a cone of 150 o.
RES ET
15 msec (minimum) negative going pulse clears display and initializes processor
power–up sequence.
(Requires current sink capable of discharging a 4.7 F internal capacitor and a 10 k
resistor to V
BUSY
High during write or hardware reset. Low when ready for data.
(Not used with serial data mode or LCD mode.)
DIMMING
10 k
internal pull–up provides hardware brightness level control.
(A 100 k
BELL
Drive output for audible signalling device. A 160 msec wide output that can sink
0.2 A from a 5.0 Vdc source.
500 msec minimum
2 X 40
1X20
036X2
036X2
–106
-120, -121
176
123
175
124
171
126
715
215
171
125
171
123
1224
755
802
765
901
270
Table 3–5
sec)
.)
CC
potentiometer is recommended.)
SIZE
CODE IDENT NO.
A
05464
SCALE
N/A
2 X 20
4 X 20
036X2
036X2
–122, -130
–124, -134
290
470
181
285
465
184
285
460
179
410
1210
746
285
460
178
285
460
176
585
1055
1260
805
1000
780
410
1445
901
S036X2–XXX–XXXXX
SHEET
N
REV
2 X 40
4X40
036X2
03602
–151
-160
350
351
350
1726
352
347
2738
711
3504
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