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3.3V
RM1
10k
1
2
3
4
3.3V
U9
R15
22
2
1
CLKA1
REF
R16
22
3
16
CLKA2
FBK
R8
22
14
CLKA3
R7
22
15
9
CLKA4
S1
8
C14
CS19
S2
6
13
CLKB1
VDD
7
12
100p
0.1u
CLKB2
GND
10
4
CLKB3
VDD
11
5
CLKB4
GND
CY2308-2
C20
CS27
100p
0.1u
R10
22
R9
22
3.3V
U8
R13
22
2
1
CLKA1
REF
R14
22
3
16
CLKA2
FBK
R6
22
14
CLKA3
R5
22
15
9
CLKA4
S1
8
C13
CS25
S2
6
13
CLKB1
VDD
7
12
100p
0.1u
CLKB2
GND
10
4
CLKB3
VDD
11
5
CLKB4
GND
CY2308-2
C19
CS17
100p
0.1u
3.3V
U6B
12
POVS*
D
11
CLK
10
PRE
13
CLR
14
VCC
TC74LCX74/SO
U6A
2
POHS*
D
3
CLK
4
PRE
1
CLR
14
VCC
TC74LCX74/SO
5
6
7
BLANK*
PSAVE*
TO 04ADV7123
MCLK0
MCLK1
MCLK2
MCLK3
L4
3.3V
NFM2012P13C474F
signal name is reverse(SCLK,DATA)
but ajustment contents in FPGA
U1
8
2
SCLKA
MCLK
SEL1/DATA
9
1
VCLK
SEL0/CLK
DATA
4
OE
10
3
ERROUT
AVDD
11
13
EXTCLK
VDD
12
INIT0
14
7
C12
C15
C10
C11
INIT1
X2
15
6
EXTSEL
X1
16
5
0.01u
0.01u
100p
0.01u
PD
GND
ICS9161A
X1
1
XIN
2
XOUT
L5
3.3V
C21
C16
14.31818MHz
15p
15p
NFM2012P13C474F
POCLK
CLOCK
9
Q
VSYNC*
8
Q
3.3V
CS20
0.1u
COMPONENT
5
Q
HSYNC*
6
Q
8
9
10
5V
L1
NFM2012P13C474F
+
C2
33u
SUB
NAME
CIRCUIT BOARD NO.
DRAWING NO.
1A860S088
11
12
13
14
A
B
C
D
E
F
G
H
I
03/04
J
KR
SCM008
15
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