Panasonic DMR-EH50EB Service Manual page 50

INITIAL/LOGO
X X X' TAL
XALE X ADDRESS LATCH ENABLE
XAREQ X AUDIO DATA REQUEST
XCDROM X CD ROM CHIP SELECT
XCS X CHIP SELECT
XCSYNC X COMPOSITE SYNC
XDS X DATA STROBE
XHSYNCO X HORIZONTAL SYNC OUTPUT
XHINT XH INTERRUPT REQUEST
XI X' TAL OSCILLATOR INPUT
XINT X INTERRUPT
XMW X MEMORY WRITE ENABLE
XO X' TAL OSCILLATOR OUTPUT
XRE X READ ENABLE
XSRMCE X SRAM CHIP ENABLE
XSRMOE X SRAM OUTPUT ENABLE
XSRMWE X SRAM WRITE ENABLE
XVCS X V-DEC CHIP SELECT
XVDS X V-DEC CONTROL BUS
STROBE
XVSYNCO
X VERTICAL SYNC OUTPUT
17. Block Diagram
17.1. Power Supply Block Diagram
17.2. Analog Video Block Diagram
17.3. Analog Audio Block Diagram
17.4. Timer Block Diagram
18. Schematic Diagram
18.1. Interconnection Schematic Diagram
18.2. Power Supply Schematic Diagram
18.3. Main Net Section (Main P.C.B. (1/3)) Schematic Diagram (M)
18.4. A/V I/O Section (Main P.C.B. (2/3)) Schematic Diagram (AI)
18.5. Timer Section (Main P.C.B. (3/3)) Schematic Diagram (T)
ABBREVIATIONS
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