Motorola MSF 5000 Instruction Manual page 93

Chapter 1 Description
MSF
5000
Instruction Manual
Uniboard
Phase-Locked Loop Circuitry
Various output frequencies
are generated
by
the synthesizer through the use of a
single negative feedback loop. The phase difference between two signals
at the
phase detector
input
controls the
VCO
output
frequency.
The two signals being
compared are the reference frequency
signal and
the loop
pulse signal.
Astable
14.4
MHz
reference signal is generated by
a
crystal oscillator element.
The
reference
divider divides
the 14.4
MHz
signal down
to a 6.25
kHz
square
wave.
A
loop pulse signal is the negative feedback signal from the
PLL.
This signal is
created
by dividing
the
VCO
output
via
the programmable loop
counter/divider.
The frequency divides
the
signal
by
the
programmed factor of
"N".
The microprocessor on
the
SSCB
reads
divider
data from the code plug.
This
divider data is multiplexed into six
4
bit data words. Each data word is loaded
into
the
divider through four separate lines (SD0 through SD3)
with
three
corresponding address lines (SAO through
SA2).
All
six data words
are
demultiplexed in
the
appropriate divider.
This
data
provides
the
divider with
the appropriate divide-by-number to obtain the desired
PLL
output
frequency.
The loop pulse and
reference
signals
are
applied
to
inputs of
the phase detector.
The phase
detector monitors the phase difference between the signals.
A
DC
control voltage is generated that is proportional to the phase difference between
the loop and reference frequencies.
The control voltage is routed through
the
adaptive loop
filter.
The adaptive
loop
filter damps the loop transient
response and attenuates noise and spurs.
The
resultant signal drives the
VCO
steering line.
The steering line signal
increases or decreases the
VCO
output frequency
as
voltage level of
the
DC
control voltage varies.
If
the
VCO
output frequency
increases, the loop
signal frequency
increases.
This causes a phase change at the
phase detector.
The phase detector then lowers the
DC
control voltage
in
accordance
with
the phase
slippage. The
DC
control voltage causes the adaptive
loop filter to adjust
the steering line
so
it
moves the
VCO
frequency back down.
Super Filter
Since the
VCO
requires
a
very
pure
DC
supply voltage,
an ultra low-pass filter
(U325) provides the Transmit
VCO
with
a
very low
noise
supply
voltage. The
IPA
provides an input voltage of
+9.6
Vdc
to the super filter.
Any
ripple or noise
present on the +9.6
Vdc
supply line is removed
by
the super
filter,
preventing unwanted modulation of the
VCO.
The filter causes
a
voltage
drop of +1
Vdc
to occur,
which
results
in
an
output voltage of
+8.6
Vdc. The
+8.6
Vdc
is used on
the
Uniboard and is also routed
to the Transmit
VCO
via
J342.
68P81092E02
3/19/94
1-54
1-54