DIGITAL (DMAIN IF) SCHEMATIC DIAGRAM
TO DMAIN
5
DAOUTA
DISCRIA
VCO19ACTL
ADCKA
TO SUB CPU
4
D_REC_L
TO DMAIN
DAOUTB
DISCRIB
VCO19BCTL
ADCKB
DAOUTREF
3
TO DMAIN
AINA
AINB
3.3VREC
RECCLK
RECDATAB
RECDATAA
2
TO SUB CPU
AT_ON
1
SW12V
SW5V
PS3.3V[A]
GND
A
2-29
DIGITAL
( DMAIN IF )
B403
OPEN
C436
0.1
IC405
SN74LV74APW-X
OPEN
B404
C446
0.1
IC406
TC7SH04FU-X
B
IC402
TLC2932-X
LOGVDD
VCOVDD
R403
SELECT
RBIAS
2.2k
VCOOUT
VCOIN
FINA
VCOGND
FINB
VCOINH
PFDOUT
PFDINH
LOGGND
NC
C404
0.1
IC404
TLC2932-X
LOGVDD
VCOVDD
R435
SELECT
RBIAS
2.2k
VCOOUT
VCOIN
FINA
VCOGND
FINB
VCOINH
PFDOUT
PFDINH
LOGGND
NC
C422
0.1
L409
10µ
T
C437
C438
22
0.01
/6.3
R465
390
Q418
2SC4081/QRS/
L412
10µ
T
C447
C448
22
0.01
/6.3
R481
390
Q423
2SC4081/QRS/
C
L401
L402
10µ
10µ
R405
10k
C407
Q429
47
OPEN
/6.3
R404
100
R406
100
R499
OPEN
C409
1µ
C408
R401
0.01
C405
OPEN
OPEN
Q401
DTC114EUA-X
L405
10µ
L406
10µ
R437
10k
C425
47
Q430
/6.3
OPEN
R436
100
R438
R416
100
OPEN
R402
C423
C426
OPEN
OPEN
1µ
R466
15k
R467
0Ω
C439
0.1
C441
L410
0.01
OPEN
R469
R468
330
56k
C440
OPEN
Q419
DTC114EUA-X
R482
15k
R483
0Ω
C449
0.1
L413
OPEN
R485
R484
330
56k
C450
OPEN
D
C410
C41
47
0.01
/6.3
R497
0Ω
R498
OPEN
C427
C42
47
0.01
/6.3