System Control Block Diagram - JVC HM-DH40000K Service Manual

SYSTEM CONTROL BLOCK DIAGRAM

CAP
DRUM MOTOR
M
5 5
1 2
A/C HEAD
A/C HEAD
CTL
TO
VIDEO/AUDIO
2-63
0
CN3003
MDA
CAP_REV ( L )
6
M
CAP_CTL_V
3
CAP_FG
2
CON1 CN3001
DRUM_CTL_V
3 3
D.PG
2 4
D.FG
1 5
LOADING MOTOR
CN3002
LDM2
M 2
LDM1
1
ROT AR Y
CN3004
ENCODER
LSB
1
LSC
2
LSA
3
CN1 CN2001
CTL HEAD ( - )
2 6
CTL HEAD ( + )
1 7
V. PULSE
VIDEO_ENV
V/STD/HS1.FF
A/HS2.FF
H.REC_ST(H)
N.REC_ST(H)
TO
A.MUTE(H)
AUDIO I/O
CN3009
HS2_FF
12
HS1_FF
11
REF30
10
TO DIGITAL
REF5
9
(HOST)
HOST_RESET
8
CN7001
KBUS_REQ 7
KBUS_CLK 6
KBUS_DATA
4
For ADJ.
CN3010
RESET 2
FWE
3
SIO
5
SII
6
Note : For the waveforms in this block diagram, refer to page 2-56.
MAIN ( SYSCON, MAIN-TERMINAL )
3
WF1
WF2
WF3
PC3001
PHOTO
SENSOR
IC3004
( LOADING MOTOR
VOLTAGE CONTROL )
2 9
LDM2 LMC1
4 7
LDM1 LMC2
1
Vref
WF5
A/HS2.FF
V/STD/HS1.FF
SIO
SII
AMP
IC4101
PC3002
PHOTO
SENSOR
DRIVE VOL T AGE
CONTROL
TP4001
Q3001
CTL.P
WF4
Q4002
ES
D3004
2 1
RESET
AL6V
IC3002
4
( RESET )
Q3013
ES
IC3001
( SYSTEM CONTROL
28
CAP REV ( L )
101
CAPPWM
8
CFG
102
DRUMPWM
107
DPG
108
DFG
54
SP FG
55
TU FG
36
LMC1
37
LMC2
38
LMC3
6
CTLAMPOUT
26
LSB
27
LSC
25
LSA
106
HI_S_FF_REW
3
CTL ( - )
1
CTL ( + )
110
V.PULSE
19
VIDEO_ENV
100
D.FF/STD.FF/HS1.FF
99
A.FF/HS2.FF
87
H.REC_ST(H)
88
N.REC_ST(H)
89
A.MUTE(H)
90
REF30
91
REF5
103
HOST_RESET
57
K-BUS-REQ
53
K-BUS-CLK
52
K-BUS-OUT
51
K-BUS-IN
66
RES
71
MODE
62
FWE