Read Circuit - Fujitsu MAB3091FC Series Maintenance Manual

5.6.3

Read circuit

The data output from the head IC is converted to a fixed level. The acquired data is then sent
to the sample and hold circuit through the electrical filter circuit. The sample and hold circuit
samples data, then the viterbi detection circuit converts the data into a Logic signal (RD). The
VFO circuit generates a clock signal synchronized with RD. Based on this clock signal and
RD signal, the 8/9 decoding circuit converts data into NRZ data, and sends data to the buffer
memory.
(1) AGC amplifier
The AGC amplifier automatically keeps the output amplitude level constant, even if the input
amplitude level changes. Even if the head output level changes with head characteristics and
outer or inner head position, the AGC amplifier output level is constant.
(2) Electrical filter circuit
The electrical filter circuit consists of several low-pass filters (LPF) that remove unwanted
high-frequency components. This filter circuit also equalizes read-signal waveforms (partial
response class 4 equalization), and has a function which boosts high frequencies.
The low pass filter's cutoff frequency and boost up gain are controlled through a parallel I/O
from the DSP. The control MPU controls the cut-off frequency and boost gain using the DSP.
This gives the optimal filter frequency characteristics matched to the transfer frequency of
each zone.
Figure 5.6 (a) shows the schematic configuration of the electrical filter circuit. Figure 5.6 (b)
is an example of frequency characteristics of the electrical filter circuit.
(3) Sample and hold circuit
The sample and hold circuit samples analog-waveform voltages according to the period of the
clock signals generated by the VFO circuit. The sample signal from the sample and hold
circuit is passed to the AGC gain controlling level detection circuit and VFO circuit.
(4) VFO circuit
The VFO circuit generates a clock signal that is synchronized with the sample and hold circuit
output signal. At data write, the VFO circuit generates a clock signal that is synchronized with
the clock signal from the synthesizer.
(5) Viterbi detection circuit
The viterbi detection circuit detects only the sample values above about 50% threshold level of
the sample and hold circuit output signal. Then this circuit decodes the nearest digital data to
actual data.
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