Dram Timing Settings - JETWAY 695AS User Manual

DRAM Timing Settings

Please refer to section 3-6-1
AGP Function Settings
Please refer to section 3-6-2
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Parity/ECC Check
This function provides parity check of memory.
The choice is either Disabled or Enabled.
3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Auto Configuration
> DIMM1 Timing Settings
> DIMM2 Timing Settings
> DIMM3 Timing Settings
DRAM Drive Control
Delay DRAM Read Latch
Memory Data Drive
SDRAM Command Drive
↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
DIMM1/DIMM2/DIMM3 Timing Settings
Please refer to section 3-6-1.1
DRAM Timing Settings
Optimized
Press Enter
Press Enter
Press Enter
Auto
0.5ns
Weak
Weak
F6:Optimized Defaults
30
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults