End of Life ......................3 Introduction ......................4 Glossary ........................... 5 Reference Documents ......................5 Ultra96-V1 Architecture and Features ..............6 List of Features ........................6 Ultra96-V1 Block Diagram ....................... 7 Functional Description ................... 8 Zynq UltraScale+ MPSoC ......................8 6.1.1...
Ultra96-V2. To help with the nomenclature, the original Ultra96 is now referred to as Ultra96-V1. The term Ultra96 may be used to refer to the family, meaning both Ultra96-V1 and Ultra96-V2.
4 Introduction The main purposes of the Ultra96-V1 Single Board Computer are: • Provide a Xilinx entry in the 96Boards community • Combine ARM processing with programmable logic in a convenient and expandable board • Showcase a wide range of potential peripherals and acceleration engines in the programmable logic that is not available from other 96Boards offerings •...
Glossary Term Definition Zynq UltraScale+ MPSoC Processing System Zynq UltraScale+ MPSoC Programmable Logic PS Multiplexed Input Output Pins Power On Reset Application Processing Unit Real-time Processing Unit Graphics Processing Unit SYSMON System Monitor High Density PL I/O Pins High Performance PL I/O Pins PMBus Power Management Bus Reference Documents...
5 Ultra96-V1 Architecture and Features This section summarizes the features of the development board, followed by functional descriptions of each circuit. List of Features The Ultra96-V1 Single Board Computer supports the following features: • Zynq UltraScale+ MPSoC ZU3EG SBVA484 •...
6 Functional Description The following sections provide brief descriptions of each feature provided on the Ultra96-V1 board. Zynq UltraScale+ MPSoC The Zynq UltraScale+ MPSoC ZU3EG device (in the SBVA484 package) contains: • Processor System (PS): Application Processing Unit Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;...
ZU3EG provides one HD bank (Bank 26) with 24 pins, one HP bank (Bank 65) with 52 pins, and another HP bank (Bank 66) with 6 pins. The PL I/Os on Ultra96-V1 are tied to the Low-Speed 96Boards Mezzanine, the High-Speed 96Boards Mezzanine, Bluetooth, and the fan.
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Table 2 – PL IO Bank 65 MPSoC Pin Number Bank MPSoC Site Name Function IO_T3U_N12_65 IO_L7N_T1L_N1_QBC_AD13N_65 Expansion IO_L7P_T1L_N0_QBC_AD13P_65 IO_L8N_T1L_N3_AD5N_65 IO_L8P_T1L_N2_AD5P_65 IO_L9N_T1L_N5_AD12N_65 IO_L9P_T1L_N4_AD12P_65 IO_L10N_T1U_N7_QBC_AD4N_65 IO_L10P_T1U_N6_QBC_AD4P_65 IO_L11N_T1U_N9_GC_65 IO_L11P_T1U_N8_GC_65 IO_L1N_T0L_N1_DBC_65 IO_L1P_T0L_N0_DBC_65 IO_L2N_T0L_N3_65 IO_L2P_T0L_N2_65 IO_L3N_T0L_N5_AD15N_65 IO_L3P_T0L_N4_AD15P_65 IO_L16N_T2U_N7_QBC_AD3N_65 IO_L16P_T2U_N6_QBC_AD3P_65 IO_L19N_T3L_N1_DBC_AD9N_65 IO_L19P_T3L_N0_DBC_AD9P_65 IO_L20N_T3L_N3_AD1N_65 IO_L20P_T3L_N2_AD1P_65 IO_L21N_T3L_N5_AD8N_65 IO_L21P_T3L_N4_AD8P_65 IO_L22N_T3U_N7_DBC_AD0N_65 IO_L22P_T3U_N6_DBC_AD0P_65...
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IO_L13N_T2L_N1_GC_QBC_65 IO_L13P_T2L_N0_GC_QBC_65 IO_L15P_T2L_N4_AD11P_65 IO_L14N_T2L_N3_GC_65 IO_L14P_T2L_N2_GC_65 VREF_65 IO_L12N_T1U_N11_GC_65 IO_L12P_T1U_N10_GC_65 IO_T1U_N12_65 IO_L6P_T0U_N10_AD6P_65 IO_L5P_T0U_N8_AD14P_65 IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 IO_L6N_T0U_N11_AD6N_65 IO_L5N_T0U_N9_AD14N_65 IO_L4N_T0U_N7_DBC_AD7N_65 IO_T0U_N12_VRP_65 Table 3 – PL IO Bank 66 MPSoC Pin Bank MPSoC Site Name Function Number IO_T3U_N12_66 HS Expansion IO_L12N_T1U_N11_GC_66 IO_L12P_T1U_N10_GC_66 IO_L11N_T1U_N9_GC_66 IO_L11P_T1U_N8_GC_66 IO_T0U_N12_VRP_66 VREF_66 Page 12...
6.1.3 PS MIOs (Banks 500, 501, 502) Table 4 – MIO Overview Bank 500 1.80V UART1 UART0 I2C1 SPI1 SPI1 WE BE PB SD0 USB Bank 501 1.80V DPAUX PMIC SPI0 PK TP SPI0 Bank 502 1.80V USB0 USB1 UART1 - Header UART0 - Bluetooth (+ PL RTS/CTS) I2C1 - I2C Hub SPI1 - HS Expansion Header...
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Table 5 – MIO Bank 500 (MIOs 0 to 25) Bank Pin # Device Signal Notes 0 UART1 MIO0_UART1_TX UART Header J6 MIO1_UART1_RX 2 UART0 MIO2_UART0_RX_BT_HCI_TX WL1831 B MIO3_UART0_TX_BT_HCI_RX 4 I2C1 MIO4_I2C1_SCL I2C Mux MIO5_I2C1_SDA 6 SPI1 MIO6_SPI1_SCLK Hi-speed Expansion Header 7 GPIO MIO7_WLAN_EN...
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Table 6 – MIO Bank 501 (MIOs 26 to 51) Bank Pin # Device Signal Notes 26 GPIO MIO26_POWER_INT_B Pushbutton On/Off Controller Interrupt, Pushbutton turn-off event detected 27 DPAUX MIO27_DP_AUX_OUT DPAUX single-ended output MIO28_DP_HPD DPAUX Hot Plug Detect MIO29_DP_OE DPAUX Output Enable MIO30_DP_AUX_IN DPAUX single-ended input 31 GPIO...
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Table 7 – MIO Bank 502 (MIOs 52 to 77) Bank Pin # Device Signal Notes 52 USB0 MIO52_USB0_CLK USB0 Clock MIO53_USB0_DIR USB0 Data bus direction MIO54_USB0_DATA2 USB0 Data 2 MIO55_USB0_NXT USB0 Data flow MIO56_USB0_DATA0 USB0 Data 0 MIO57_USB0_DATA1 USB0 Data 1 MIO58_USB0_STP USB0 Stop transfer MIO59_USB0_DATA3...
6.1.4 PS Bank 503 Mode, config, PSJTAG, error, SRST, and POR. Bank 503 contains system-level pins, including Table 8 – PS Bank 503 MPSoC Pin Bank MPSoC Site Name Number PS_ERROR_OUT_503 PS_ERROR_STATUS_503 PS_INIT_B_503 PS_MODE1_503 PS_MODE2_503 PS_MODE3_503 PS_PADI_503 PS_PADO_503 PS_POR_B_503 PS_REF_CLK_503 PS_SRST_B_503 Page 17...
6.1.5 PS Bank 504 Bank 504 contains the DDR Controller pins which are connected to LPDDR4 on Ultra96-V1. Table 9 – PS Bank 504 MPSoC Pin Bank MPSoC Site Name Number AA22 PS_DDR_A0_504 AB20 PS_DDR_A1_504 AB17 PS_DDR_A2_504 AB19 PS_DDR_A3_504 AB21...
MT53B512M32D2NP-062 WT:C. microSD Card Ultra96-V1 provides a microSD card socket as the primary boot device. VCCO for MIO1 is 1.80V thus a level shifter is required. A Maxim MAX13035E is used. When available, the Ultra96-V1 kit ships with a Delkin Devices “Utility” 16 GB Industrial MLC microSD card, pre-programmed with Linux boot.
Ultra96-V1 provides one upstream (device) and two downstream (host) USB 3.0 connections. A USB 2.0 downstream (host) interface is provided on the high speed expansion bus. Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS USB Controller Hub are specified.
Ultra96-V1 supports one Mini DisplayPort output. A TE Connectivity 2129320-3 provides the Mini DisplayPort connectivity. UART Ultra96-V1 provides access to one UART on the baseboard. PS UART1 (MIO0, MIO1) is connected to a 3-pin 2mm header (J6). Table 12 – Pinout for the J6 UART Header...
6.10 MPSoC Thermal Bracket with Fan The Ultra96-V1 uses a thermal bracket with fan for the MPSoC device. The bracket is mounted to the bottom side of the Ultra96-V1 to help dissipate heat. A Sunon MC30060V1-000U-A99 fan is used, connected to 5V and GND at J18 and J19. Users can control the fan using signal FAN_PWM from PL IO F4 on Bank 65.
Amphenol FCI 61082-061409LF (or compatible) 60 pin low profile 0.8mm receptacle is specified. Table 14 shows the pinout of the High Speed Expansion Header (Ultra96-V1 column) and the differences from the 96Boards specification (96Boards column). With the exception of SD, I2C2 and I2C3, all dedicated interfaces specified by 96Boards are replaced with GPIO.
7 Configuration and Debug Boot Mode Ultra96-V1 supports booting from JTAG and microSD Card. A DIP switch (SW2) is installed to allow selecting the desired boot mode. Figure 5 – Boot Mode Switch (SD Boot Mode Shown) JTAG Configuration and Debug JTAG access to the MPSoC is available through a 1x7 header (J2).
EIAJ-3 compliant DC plug available up to 2A, which is 4.75 mm outer diameter with 1.7mm center pin (4.75/1.7), for the power supply • https://en.wikipedia.org/wiki/EIAJ_connector However, there is a bit of flexibility. Avnet offers a 12V supply as an accessory (part number: AES-ACC-U96-4APWR) with the following specifications: • Input: AC 100-240v, 50/60HZ •...
Power Estimator (XPE) spreadsheet is available on Xilinx’ website that can help you get started with your own power estimation. Avnet has also provided an example of this spreadsheet filled out for the Ultra96-V1 under Documentation on the Ultra96-V1 website.
3.3 V 2 ms BUCK4 (VCC_3V3) CTL3 (PS_LP_PWR_EN) CTL5 (PL_PWR_EN) GPO4 (VCCINT enable) 1.8 V 2 ms SWB1_2 (VCCAUX) 1.2 V 2 ms LDOA3 (VCCO_HP) CTL1 (PS_POR_PB_B) 2.5 ms 2.5 ms GPO3* (PS_POR_B) Figure 9 – Ultra96-V1 Power Sequencing Page 30...
These clocks are generated by a Customizable Quad Clock Generator. 10 Reset Ultra96-V1 Reset is managed by the TI PMIC. At power-up, the ZU3EG is held in reset until all power rails have ramped up and are stable. A pushbutton allows manually resetting the ZU3EG.
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