Avnet SMARC MSC SM2S-IMX8M User Manual
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Avnet SMARC MSC SM2S-IMX8M User Manual

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User Manual
SMARC™ Module
MSC SM2S-IMX8M
SMARC Rev. 2.0 Standard
Version 1.1
18.03.2021

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Summary of Contents for Avnet SMARC MSC SM2S-IMX8M

  • Page 1 User Manual SMARC™ Module MSC SM2S-IMX8M SMARC Rev. 2.0 Standard Version 1.1 18.03.2021...
  • Page 2 Preface Copyright Notice Copyright © 2021 MSC Technologies GmbH. All rights reserved. Copying of this document, and providing to others and the use or communication of the contents thereof, is forbidden without express authority of MSC Technologies GmbH. Offenders are liable to the payment of damages. All rights are reserved in the event of the grant of a patent or the registration of a utility model or design.
  • Page 3 Certification MSC Technologies GmbH is certified according to DIN EN ISO 9001:2000 standards. Life-Cycle-Management MSC products are developed and manufactured according to high quality standards. Our life-cycle-management assures long term availability through permanent product maintenance. Technically necessary changes and improvements are introduced if applicable.

  • Page 4: Table Of Contents

    Contents INTRODUCTION ........................................11 Key Features ..............................................11 Block Diagram ............................................... 15 Power Supply ..............................................16 Power Consumption ............................................16 1.4.1 Use Cases ..................................................16 1.4.2 Hardware used ................................................17 1.4.3 Measurement Results ..............................................17 Mechanical Dimensions ..........................................18 Mechanical Deflection of PCB ........................................19 THERMAL SPECIFICATIONS....................................
  • Page 5 5.3.2 eMMC .................................................... 49 5.3.3 EEPROM ..................................................50 Trusted Platform Module ..........................................51 WiFi Module ..............................................51 Debug Options ............................................... 52 5.6.1 LEDs....................................................52 5.6.2 Debug Connector ................................................53 5.6.3 JTAG Connector ................................................55 BUS AND ADDRESS MAPPING ..................................57 I²C Devices ..............................................
  • Page 6 Figure 1-1: Block Diagram ............................................15 Figure 1-2: Module Dimensions ..........................................18 Figure 1-3: Overall Height without heat spreader of the SMARC™ Module ............................. 18 Figure 1-4: Distance between mounting holes ......................................19 Figure 2-1: Temperature measuring point on PCB ....................................21 Figure 5-1: CPU Options ............................................
  • Page 7 Figure 7-32: Bug report. User message editor ......................................85 Figure 7-33: Bug report. Viewer page ........................................86 Figure 7-34: Bug report. Content selector ......................................... 87 Figure 7-35: Bug report. Partition selector......................................... 88 Table 1-1: Module Power Inputs ..........................................16 Table 1-2: Modules Used for Power Consumption Measurement ................................17 Table 1-3: Power Consumption Measurement ......................................
  • Page 8 Revision History Rev. Date Description February 9 , 2021 First Release March 18, 2021 Several fixes MSC SM2S-IMX8M User Manual 8 / 92...
  • Page 9 Reference Documents SMARC™ Specification Revision 2.0 Last update: June 2nd 2016 http://www.sget.org IEEE Std. 802.3-2002 802.3-2002.pdf http://www.ieee.org Universal Bus Specification usb_20.pdf Last update: April 27th, 2000 http://www.usb.org i.MX 8M Series of Application Processors IMX8MDQLQIEC.pdf http://www.nxp.com Module Datasheet MSC-SM2S-IMX8M.pdf https://www.msc-technologies.eu/support/boards/smarc/msc-sm2s-imx8m.html i.MX Reference Manual. i.MX_Linux_Reference_Manual.pdf Version: L4.9.51_imx8mq-ga, 03/2018 http://www.nxp.com...
  • Page 10 i.MX Porting Guide i.MX_Porting_Guide.pdf Version: L4.14.98-2.0.0_ga, 04/2019 http://www.nxp.com i.MX Yocto Project User's Guide() [10] i.MX_Yocto_Project_User's_Guide.pdf Version: L4.14.98-2.0.0_ga, 04/2019 http://www.nxp.com i.MX Linux® Release Notes [11] i.MX_Linux_Release_Notes.pdf.pdf Version: L4.14.98-2.0.0_ga, 05/2019 http://www.nxp.com Docker documentation [12] https://docs.docker.com/ MSC SM2S-IMX8M User Manual 10 / 92...

  • Page 11: Introduction

    1 Introduction SMARC™ modules are compact, highly integrated Single Board Due to the standardized mechanics and interfaces the system can be Computers. scaled arbitrarily. Despite the modular concept the system design is very flat and compact. Typically a SMARC™ module consists of a CPU, chipset, memory, Ethernet controller, BIOS flash, SATA- and USB controller.
  • Page 12 Audio:  2x I²S links for audio codec connection Camera Interface:  2x MIPI CSI-2 (4 Lane / 2 Lane) PCI Express Interface:  2x PCIe x1 Gen.2 Lane Network:  1x 10/100/1000BASE-T Ethernet  Optional: HD Wireless Module SPB228, MU-MIMO 2x2 with 802.11 ac/a/b/g/n and Bluetooth/BLE support, soldered on module USB: ...
  • Page 13 SPI:  Up to 2x SPI with 2 chip selects each NOTE: CAN and SPI are mutual exclusive  Optional QSPI NOR Flash (population option on module only) I²C Bus:  I²C and SM-Bus for Power Management functions  I²C bus for general purpose ...
  • Page 14 CAN:  Up to 2x CAN 2.0B (Controller Area Network) at 1Mbps NOTE: Quantity of UART interfaces with RTS/CTS support is dependent on SPI/CAN, mutual exclusive option NOTE: CAN and SPI are mutual exclusive Real-time Clock:  Module provides a high accuracy RTC ...

  • Page 15: Block Diagram

    1.2 Block Diagram Figure 1-1: Block Diagram MSC SM2S-IMX8M User Manual 15 / 92...

  • Page 16: Power Supply

    1.3 Power Supply Table 1-1: Module Power Inputs Power Rail Description VDD_IN Primary power input Nominal Voltage Range +4.75V ... +5.25V Max. Input Ripple ±100mV Rate of Voltage Rising < 250V/s VDD_RTC May be sourced from a Lithium cell or a Super Cap. Nominal Voltage Range +1.5V ...

  • Page 17: Hardware Used

    1.4.2 Hardware used Table 1-2: Modules Used for Power Consumption Measurement Order Number Reference Temp. Range 73289 MSC SM2S-IMX8M-DC-03N0600I PCBFTX 8M Dual, Dual-Core Cortex-A53 at 1.3Ghz 1G LPDDR4 -40°C to +85°C 73301 MSC SM2S-IMX8M-QCL-13N0600I PCBFTX 8M QuadLite, Quad-Core Cortex-A53 at 1.3Ghz 2G LPDDR4 -40°C to +85°C...

  • Page 18: Mechanical Dimensions

    1.5 Mechanical Dimensions Figure 1-2: Module Dimensions Figure 1-3: Overall Height without heat spreader of the SMARC™ Module TOP Side – Component 3.0mm max 5.7mm min Module PCB 1.2mm BOT Side – Component 1.3mm max 1.5mm min Carrier PCB The overall height is dependent on the selected MXM3 connector used on the baseboard. MSC SM2S-IMX8M User Manual 18 / 92...

  • Page 19: Mechanical Deflection Of Pcb

    1.6 Mechanical Deflection of PCB For thermal heat dissipation the heat sink needs to be pressed onto the CPU. The higher the pressure the lower is the thermal transition resistance and consequently the better the thermal cooling. This pressure may result in a slight mechanical bending of the SMARC module. Production tolerance, material deviation and thermal expansion lead to a range of possible pressure and bending.

  • Page 20: Thermal Specifications

    2 Thermal Specifications The cooling solution for a SMARC™ module is based on a heat spreader or heat-sink concept. A heat spreader or heat sink is typically made of aluminum mounted on top of the module. The connection between this plate and the module components is made using thermal interface materials such as phase change foils, gap pads and copper or aluminum blocks.
  • Page 21 The temperature at the defined point on the PCB shall not exceed the temperature range in the following table. Table 2-1: Temperature Range Module Variant Tpcb_min Tpcb_max Module variants with commercial temperature components 0 °C +70 °C Module variants with extended temperature components -25 °C + 85 °C Module variants with industrial temperature components...

  • Page 22: Module Connector Pinout

    3 Module Connector Pinout The pinning of the module connector is based on the SMARC™ specification[1]. Table 3-1: Module Connector Pinout Primary (Top) Side Secondary (Bottom) Side Primary (Top) Side Secondary (Bottom) Side SMB_ALERT_1V8# I2C_CAM1_CK I2C_CAM1_DAT GBE0_MDI3- CSI1_CK+ GBE0_MDI3+ CSI1_CK- GBE0_LINK100# I2C_CAM0_CK GBE0_LINK1000#...
  • Page 23 Primary (Top) Side Secondary (Bottom) Side Primary (Top) Side Secondary (Bottom) Side SDIO_CD# USB4+ SPI1_CK SDIO_CK USB4- SPI1_DO SDIO_PWR_EN SPI1_DIN AUDIO_MCK SDIO_D0 I2S0_LRCK USB0+ SDIO_D1 I2S0_SDOUT USB0- SDIO_D2 I2S0_SDIN USB0_EN_OC# USB3_SSTx+ SDIO_D3 I2S0_CK USB0_VBUS_DET USB3_SSTx- SPI0_CS0# USB0_OTG_ID SPI0_CK USB1+ USB3_SSRx+ SPI0_DIN USB1- USB3_SSRx-...
  • Page 24 Primary (Top) Side Secondary (Bottom) Side Primary (Top) Side Secondary (Bottom) Side PCIE_A_RST# PCIE_B_RST# HDMI_D1- DP0_LANE1- USB4_EN_OC# DP0_HPD CPU_TCK HDMI_D0+ DP0_LANE2+ CPU_TDO HDMI_D0- S100 DP0_LANE2- P100 S101 P101 HDMI_CK+ S102 DP0_LANE3+ P102 HDMI_CK- S103 DP0_LANE3- P103 S104 PCIE_A_REFCK+ PCIE_B_REFCK+ P104 HDMI_HPD S105 DP0_AUX+...
  • Page 25 Primary (Top) Side Secondary (Bottom) Side Primary (Top) Side Secondary (Bottom) Side P117 GPIO9 S118 LVDS1_2- / DSI1_D2- P138 SER2_RTS# S139 I2C_LCD_CK P118 GPIO10 S119 P139 SER2_CTS# S140 I2C_LCD_DAT P119 GPIO11 S120 LVDS1_3+ / DSI1_D3+ P140 SER3_TX S141 LCD0_BKLT_PWM P120 S121 LVDS1_3- / DSI1_D3- P141...

  • Page 26: Module Connector Signal Description

    4 Module Connector Signal Description In the following tables signals are marked with the power rail associated with the pin, and for input and I/O pins, with the input voltage tolerance. The pin power rail and the pin input voltage tolerance may be different.
  • Page 27 4.1 I²S The module provides two I²S Links for connecting I²S codecs on the carrier board. Driver support for I²S is only available for Linux. Some features: • Programmable data interface modes such as I2S, LSB or MSB-justified • Programmable word length (16, 20, 24 or 28bits) •...

  • Page 28: Ethernet

    4.2 Ethernet Based on Texas Instruments™ DP83867 Ethernet controller the module provides 10/100/1000 Mbps Ethernet with MDI differential pairs for an external transformer. The DP83867 includes a voltage mode line driver so it doesn’t require an analog powered center tap. Therefore Pin P28 GBE0_CTREF specified in the SMARC™...

  • Page 29: Pci Express

    4.3 PCI Express The i.MX8M SoC supports two PCIe x1 Gen2 lanes. Please note, that only single channel (x1) interfaces are supported. Table 4-3: PCIe Signal Description Signal Pin on Power Signal Pin Type Pin name on i.MX8M PU/PD Description Level i.MX8 Tolerance...

  • Page 30: Usb

    Signal Pin on Power Signal Pin Type Pin name on i.MX8M PU/PD Description Level i.MX8 Tolerance PCIE_WAKE# 3.3V SAI1_MCLK 3.3V PU 10k PCI Express Wake signal. Asserted by CMOS device when requesting wake up. (CPU GPIO4_IO20) NOTE: PCIE_A_RST# and PCIE_B_RST# share same CPU pin. 4.4 USB The USB controller supports USB 3.0 and USB 2.0.
  • Page 31 Power Option Pin on Pin name on Signal Pin Type Signal Level Toleranc PU/PD Description Availability i.MX8M i.MX8M USB1+ n.a. n.a. 3.3V Differential USB 2.0 data pairs USB1- connected to USB hub. Can be configured as host only. USB2_DP 3.3V Differential USB 2.0 data pairs connected to SoC.

  • Page 32: Camera

    Power Option Pin on Pin name on Signal Pin Type Signal Level Toleranc PU/PD Description Availability i.MX8M i.MX8M USB3_EN_OC# I/O OD 3.3V CMOS n.a. n.a. 3.3V PU 10k 3.3V Multi-function signal for enabling USB power and indicating an over- current event. USB4_EN_OC# I/O OD 3.3V CMOS...
  • Page 33 Signal Pin on Pi name on Power Signal Pin Type PU/PD Description Level i.MX8M i.MX8M Tolerance CSI1_D[2]- 1.8V CMOS MIPI_CSI2_D2_N 1.8V CSI differential data inputs CSI1_D[2]+ MIPI_CSI2_D2_P CSI1_D[3]- 1.8V CMOS MIPI_CSI2_D3_N 1.8V CSI differential data inputs CSI1_D[3]+ MIPI_CSI2_D3_P CSI0_CK+ 1.8V CMOS MIPI_CSI1_CLK_N 1.8V CSI differential clock inputs...

  • Page 34: Lvds

    4.6 LVDS LVDS is optionally available and is mutually exclusive with the DSI option. LVDS channels 0 and 1 are available on the SMARC™ module depending on module variant. An on-module DSI bridge converts the MIPI DSI data stream to one Single-Link LVDS or one Dual-link LVDS. Features: ...
  • Page 35 Signal Pin on Pin name on Power Signal PU/PD Description Type Level i.MX8M i.MX8M Tolerance LVDS1_2+ / DSI1_D2+ LVDS n.a. n.a. 2.8V LVDS Channel 1 differential pair LVDS1_2- / DSI1_D2- LVDS1_3+ / DSI1_D3+ LVDS n.a. n.a. 2.8V LVDS Channel 1 differential pair LVDS1_3- / DSI1_D3- LVDS1_CK+ / DSI1_CLK+ LVDS...

  • Page 36: Hdmi/Dp

    4.7 HDMI/DP An on-module MUX/DEMUX provides HDMI and DisplayPort signal switching. Both interfaces are available on the SMARC™ module and can be selected via software. The two options are mutually exclusive. Supported interfaces:  HDMI 2.0a up to 4096x2160  DisplayPort 1.3 up to 4096x2160 Table 4-7: HDMI/DP Signal Description Signal...

  • Page 37: Spi Bus

    4.8 SPI Bus The i.MX8M SMARC module offers two Enhanced Configurable SPI (ECSPI) busses with two slave select signals each. Key features of the ECSPI include: • Full-duplex synchronous serial interface • Two Chip Select (CS) signals to support multiple peripherals •...

  • Page 38: Can

    4.9 CAN The i.MX8M SMARC module features two CAN interfaces based on the MCP2515 stand-alone controller. MCP2515 implements CAN 2.0B protocol specification with up to 1Mbps bit rate. Standard and extended data and remote frames are supported. Several features are supported (time-triggered protocols, data byte filtering and one-shot mode). Table 4-9: CAN Signal Description Signal Pin on...

  • Page 39: Gpio

    4.10 GPIO The CPU GPIO can be used with default Linux GPIO SYSFS interface in user space. Table 4-10: GPIO Signal Description Signal Pin on Pin name on Power Signal PU/PD Description Type Level i.MX8M i.MX8M Tolerance GPIO0 / CAM0_PWR# 1.8V CMOS GPIO1_IO00 1.8V...

  • Page 40: Sdio

    4.11 SDIO The SDIO interface on the SMARC™ connector supports:  1-bit / 4-bit for SD/SDIO mode (standard up to version 3.0)  1-bit / 4-bit for MMC mode (standard up to version 5.1)  SD/SDIO 1.8 V (UHS-I) or 3.3 V operation with auto detection ...

  • Page 41: Uart

    4.12 UART The i.MX8M offers several UART interfaces. Depending on module variant up to four separate interfaces are linked to the SMARC™ connector, two of them with Hardware flow control support signals. The UART interfaces supports Serial RS-232NRZ mode, 9-bit RS-485 mode or IrDA mode and includes the following features amongst others: •...
  • Page 42 Power Signal Pin on Pin name on Signal Pin Type Toleranc PU/PD Description Level i.MX8M i.MX8M SER0_RTS# 1.8V CMOS UART3_RXD 1.8V PU 10k 1.8V UART handshake, ready to receive data SER0_CTS# 1.8V CMOS UART3_TXD 1.8V PU 10k 1.8V UART handshake, ready to send data SER1_TX 1.8V CMOS UART2_TXD...

  • Page 43: I²C Bus

    4.13 I²C Bus I2C_GP on the SMARC™ connector is also linked to an on-module EEPROM at address 0x50. For further I²C bus signals see also Camera, HDMI, LCD/LVDS and System Management interfaces. The I²C bus driven by CPU core function has the following key features: •...

  • Page 44: Watchdog

    4.14 Watchdog Table 4-14: Watchdog Signal Description Pin name Signal Pin on Power Signal Pin Type PU/PD Description Level i.MX8M Tolerance on i.MX8M WDT_TIME_OUT# O PP 1.8V CMOS GPIO1_IO02 1.8V Watch-Dog-Timer Output from the SOC. 4.15 System Management Table 4-15: System Management Signal Description Signal Pin on Pin name on...
  • Page 45 Signal Pin on Pin name on Power Signal PU/PD Description Type Level i.MX8M i.MX8M Tolerance CHARGING# 1V8 CMOS 1.8V PU 10k 1V8 Held low by Carrier during battery charging. Carrier to float the line when charge is complete. Pulled up on Module. Driven by OD part on Carrier.

  • Page 46: Boot-Options

    4.16 Boot-Options Table 4-16: Boot Options Control Signal Description Signal Pin on Pin name on Power Signal Pin Type PU/PD Description Level i.MX8M i.MX8M Tolerance BOOT_SEL0# I OD 1.8V CMOS SAI5_RXD2 1.8V PU 10k 1.8V Input straps determine the module boot device. Pulled up on Module.
  • Page 47 cannot be changed as it is configured by the ROM code in the CPU). When a system is booted in this way, HDMI and DP display interfaces are not operational, and the board is in an invalid condition. If TEST# signal is pulled low at carrier, the module boots from carrier SD-Card directly. Table 4-17: Boot Options BOOT_SEL2# BOOT_SEL1#...

  • Page 48: Functions On Module

    The module can be ordered with several i.MX8M CPU types. Detailed information is provided in the module datasheet which can be downloaded from https://www.msc-technologies.eu/support/boards/smarc/msc-sm2s-imx8m.html. For details regarding the i.MX8M CPU please refer to the NXP website (see[4]). For order information please contact Avnet Integrated /MSC. Figure 5-1: CPU Options...

  • Page 49: Start-Up And Power-Down Behaviour

    5.2 Start-Up and Power-Down Behaviour The module will behave in the following ways:  When coming from complete power off (5V unpowered), the module will boot if VIN_PWR_BAD# is high and 5V is present.  When OS is shut down and 5V is still powered, a power button press is required to restart the module. ...

  • Page 50: Eeprom

    Table 5-2: Available eMMC devices Chip Identification Memory Size Technology Operating Temperature Extended 8 GB 15nm X2 eMLC -25°C to +85°C SDINBDG4-8G-I1 16 GB 15nm X2 eMLC -25°C to +85°C SDINBDG4-16G-I1 32 GB 15nm X2 eMLC -25°C to +85°C SDINBDG4-32G-I1 64 GB 15nm X2 eMLC -25°C to +85°C...

  • Page 51: Trusted Platform Module

    5.4 Trusted Platform Module The i.MX8M SMARC™ module offers an optional Trusted Platform Module (TPM) from Infineon. The Infineon TPM SLB9671 2.0 is connected to the I2C4 bus at address 0x20. NOTE: Current revision of the module integrates the Infineon TPM SLB9645 1.2. 5.5 WiFi Module The i.MX8M SMARC™...

  • Page 52: Debug Options

    5.6 Debug Options 5.6.1 LEDs The module features three LEDs which display the module status. The Software-LED (yellow colour) is connected to one pin of the i.MX8M CPU. ThisLED is switched off when boot loader boot process has finished successfully. Other usage options are possible, . Table 5-3: SW LED Signal Description Signal Pin on...

  • Page 53: Debug Connector

    5.6.2 Debug Connector Access to the Debug UART port is possible via an 8pin FFC connector. Note: This connector may not be populated on all board variants. Figure 5-3: Module top side with debug UART FFC connectors marked in red Pinout: Ground Debug_2...
  • Page 54 Figure 5-4: Module top side with MSC UART debug adapter MSC Debug Adapter Order Part No. 40402 Debug UART Adapter for i.MX8-based SMARC, Qseven and nanoRISC modules, with 8-pin FFC cable to connect COM module to 9-pin D-Sub connector Use top / top cables. Serial Debug Console Output options The Debug connector offers the same SER0_RX/TX signals which are also duplicated on the SMARC connector, pins P129/130 (there with 1.8V level, while on Debug connector with 3.3V TTL level).

  • Page 55: Jtag Connector

    JTAG access to the i.MX 8M CPU is possible via a 10pin FFC connector. The JTAG Chain only contains the CPU itself, so all suitable JTAG debuggers should work with their default configuration for the respective CPU. Please contact Avnet Integrated / MSC Technical Support if this feature is required. Figure 5-5: Module top side with JTAG FFC connectors marked in red...
  • Page 56 Figure 5-6: Module bottom side with MSC JTAG debug adapter MSC JTAG-Adaptor FFC 10pol Order Part No. 68948 Debug JTAG Adapter for i.MX8-based SMARC modules, with 10-pin FFC cable to connect COM module to connectors for JTAG connection to Lauterbach and/or Goepel debuggers Use top / top cables.

  • Page 57: Bus And Address Mapping

    6 Bus and Address Mapping 6.1 I²C Devices Table 6-1: I²C Interfaces Overview CPU Interface Device SMARC Connector 7 bit Address I2C1 I2C_PM I2C2 EEPROM I2C_GP 0x50 I2C3 I2C_LCD I2C4 0x20 PMIC1 0x30 PMIC2 0x31 Temp. Sensor 0x71 0x32 PCIe Clock Generator 0x6B DSI to LVDS Bridge 0x2D...

  • Page 58: Spi Devices

    6.2 SPI Devices Table 6-2: SPI Interfaces Overview CPU Interface Chip Select CPU Pin CPU Pin Name Device SMARC Connector Description ECSPI1 ECSPI1_SS0 CAN1 Controller Dedicated chip select for CAN1 Controller NAND_DATA04 SP1_CS0# GPIO based chip select (CPU GPIO4_IO10) SAI1_RXD4 SP1_CS1# GPIO based chip select (CPU GPIO4_IO06)

  • Page 59: Board Support Package (Bsp)

    7 Board Support Package (BSP) 7.1 General information MSC-LDK and the underlying NXP release are based on the Yocto build system (https://yoctoproject.org). 7.2 The current MSC-LDK and the msc-sm2s-imx8m BSP base on NXP’s release L4.14.98-2.0.0_ga.MSC-LDK (Yocto) This chapter describes how to build an image for an msc-sm2s-imx8m module by using the MSC-LDK. 7.2.1 MSC-LDK Terms The Yocto-based MSC-LDK uses a sophisticated approach to generate Linux images.
  • Page 60 Registration on the MSC Git Server Downloading files from the MSC Git server requires a registration on: http://www.msc-technologies.eu/register.html Registered users may apply for specific Git repositories by sending an email with their public SSH key and desired project name to: mailto:support@msc-technologies.eu Creating SSH key If there is no SSH key already available ( /.ssh/id_rsa.pub), it can be generated with following command :...
  • Page 61 Make sure to keep the Private Key "id_rsa" well secured. It is generally possible to share one keypair within one and the same project, to allow several people access to the MSC sources. But then the validated user is responsible to keep track of the Private Key any time, and MUST inform MSC Support if the key has been compromised and access must be withdrawn.

  • Page 62: Setup The Msc-Ldk Build Environment

    7.2.3 Setup the MSC-LDK build environment The MSC-LDK must be installed on a partition with at least 128 GB free space. As a lot of source files will be accessed, it is recommended to use an EXT4 partition with the mount options "noatime,nodiratime".
  • Page 63 Example: Figure 7-4: Create build directory Your current directory now looks like this: Figure 7-5: Base directory content after setup build directory Step 3: Enter build directory To enter the build directory execute: cd build/0102901 MSC SM2S-IMX8M User Manual 63 / 92...
  • Page 64 Example: Figure 7-6: Enter build directory The “docker” method We assume that the docker packages (docker, docker.io, etc.) are already installed on your development system and your local user is a member of the docker group. Using "docker" may especially be helpful under newer versions of the host's OS, such as Ubuntu 18.04 LTS or higher. For detailed information about docker installation, container handling and development under docker please take a look at [12].
  • Page 65 Example: Figure 7-7: Create docker container for MSC-LDK. Part 1 MSC SM2S-IMX8M User Manual 65 / 92...
  • Page 66 Figure 7-8: Create docker container for MSC-LDK. Part 2 Step 2: Start and enter the MSC-LDK container for the first time Execute (on Debian, Ubuntu, Mint, etc.): docker run --privileged -t -i --dns $(nmcli -f 'IP4.DNS' \ -m multiline device show 2>&1 | sed -rn 's/IP4.DNS\[1\]: *(.*)/\1/p') \ --name msc-ldk -h docker -v `pwd`/src:/src msc-ldk /bin/bash Example: Figure 7-9: Start and enter the MSC-LDK container...
  • Page 67 Example: (Note: Example Screenshots still show v1.4.0) Figure 7-10: Clone and enter the base MSC-LDK repo Step 4: Create build directory Execute: ./setup.sh --bsp=0102901 Example: Figure 7-11: Create build directory MSC SM2S-IMX8M User Manual 67 / 92...
  • Page 68 Step 5: Enter build directory Execute: cd build/0102901 Example: Figure 7-12: Enter build directory Leave the MSC-LDK container. Execute: exit Example: Figure 7-13: Leave the MSC-LDK container MSC SM2S-IMX8M User Manual 68 / 92...
  • Page 69 Re-start and re-enter the MSC-LDK container. Execute: docker container start msc-ldk docker container exec -ti msc-ldk /bin/bash Example: Figure 7-14: Re-start and re-enter the MSC-LDK container Stop the MSC-LDK container and release its resources. Execute: docker stop msc-ldk docker rm msc-ldk Example: Figure 7-15: Stop the MSC-LDK container and release its resources.

  • Page 70: Generate Images

    7.2.4 Generate images Choosing an MSC-LDK image The MSC-LDK provides different images for the sms2-imx8m module. The following table lists all currently available images, their contents and sizes. Table 7-1: Available images Image name Content Approx size msc-image-minimal A small image that only allows a device to boot. 352 MiB Contains MSC features.
  • Page 71 Example: Figure 7-16: Building msc-image-base For more details and further information see also [10], Chapter 5 “Image build” . MSC SM2S-IMX8M User Manual 71 / 92...
  • Page 72 Some scripts of the recipes use an ’echo -e <somewhat>’ command. bitbake calls the buildscripts with /bin/sh as shell. If your hostsystem uses "bash" as "/bin/sh" everything works fine. But if a shell with less functionality like "dash" is used, it is necessary to setup "bash"...

  • Page 73: Image Deployment

     The setup tool allows to checkout exactly these layers and configure the BSP as before. To use it, call setup.py with only one argument -- version-file, e.g. ./setup.py --version-file ~/version_layer Modifications of conf/local.conf are not traced. This will checkout exactly the versions used by version_layer. It is then no longer possible to use scripts/update.py to pull the latest changes on the branch.
  • Page 74 Figure 7-18: SPL boot selector on EP1 carrier board (S2801). Forced carrier SD card boot mode Example: Figure 7-19: Forced SPL boot from carrier SD card Booting SPL/U-Boot from module eMMC flash The i.MX 8M boot ROM code uses the module eMMC flash as primary and the carrier SD card as secondary (fallback) boot media. The fall back media is always selected, when booting from primary media is not possible (empty, corrupted, etc.) MSC SM2S-IMX8M User Manual 74 / 92...
  • Page 75 Figure 7-20: SPL boot selector on EP1 carrier board (S2801). eMMC flash boot mode (default) Example: Figure 7-21: SPL boot from module eMMC flash Booting SPL from USB Not supported yet (see section 8.1.3) MSC SM2S-IMX8M User Manual 75 / 92...

  • Page 76: Booting Os

    7.3.2 Booting OS According to [1], chapter 4.17 “boot select” the BOOT_SEL [0:2] pins are used to select one of the following OS boot schema. Booting OS from carrier SD card In this configuration the Linux kernel image (Image) and the device tree blob are loaded from the first partition on the carrier SD card. The second partition contains the Linux file system (FS, ext4).
  • Page 77 Booting OS from module eMMC flash In this configuration the Linux kernel image (Image) and the device tree blob are loaded from the first partition on the module eMMC flash. The second partition contains the Linux file system (FS, ext4). Figure 7-24: OS boot selector on EP1 carrier board (S2802).
  • Page 78 Booting OS from Net (Ethernet) In this configuration the Linux kernel image (Image) and the device tree blob are loaded from the TFTP-, and the Linux file system is mounting on NFS-Server on LAN. Figure 7-26: OS boot selector on EP1 carrier board (S2802). Network/Ethernet boot mode.
  • Page 79 Example: Figure 7-28: OS boot from network MSC SM2S-IMX8M User Manual 79 / 92...
  • Page 80 Booting OS from USB Not support yet (see 8.1.3) In this configuration the Linux kernel image (Image) and the device tree blob are being loaded from the first partition on the USB. The second partition contains the Linux file system (FS, ext4). Figure 7-29: OS boot selector on EP1 carrier board (S2802).
  • Page 81 Available device tree blobs (DTBs) Table 7-2: Available DT blobs. Comment msc-sm2s-imx8m-dc-13N0600I.dtb i.MX 8M dual core, headless msc-sm2s-imx8m-dc-13N0600I-hdmi.dtb i.MX 8M dual core, HDMI up to 4K support msc-sm2s-imx8m-dc-13N0600I-lcdif-lvds-ama121a1.dtb i.MX 8M dual core, LVDS (bridge) amd AMA121A1 (1280x800) panel support msc-sm2s-imx8m-qc-13N0600I.dtb i.MX 8M quad core, headless msc-sm2s-imx8m-qc-13N0600I-hdmi.dtb i.MX 8M quad core, HDMI up to 4K support...

  • Page 82: Login To Fs

    7.3.3 Login to FS Login is enabled via serial console (115200 baud/8 bits/no parity). All images also have telnet login enabled. Table 7-3: Available user accounts Account Password Comment root mscldk Root user Standard user with sudo permissions. MSC SM2S-IMX8M User Manual 82 / 92...

  • Page 83: Smarc Gpio Access

    7.3.4 SMARC GPIO access According to [1] following GPIOs are available on sms2-imx8m module: Table 7-4: Available SMARC GPIOs IMX GPIO Linux/U-Boot idx ‘mscio-cmd’ alias SMARC GPIO Comment (Bank-1)*32+Id Bank Not available if CAM0 populated GPIO0 GPIO0 GPIO1 GPIO1 Not available if CAM1 populated Not available if CAM0 populated GPIO2 GPIO2...

  • Page 84: Bug Reporting

    7.3.5 Bug Reporting To simplify collecting information necessary for effectively responding to bug reports, please use the msc_bug_report.sh tool to generate bug report message. It will collect all necessary information like hardware description/configuration, kernel logs etc.  Run msc_bug_report.sh. Figure 7-31: Bug report. Main page MSC SM2S-IMX8M User Manual 84 / 92...
  • Page 85  Select “Edit User Message”. Figure 7-32: Bug report. User message editor MSC SM2S-IMX8M User Manual 85 / 92...
  • Page 86  Enter bug report message and press Ctrl-O and Ctrl-X.  Optionally you can then view the message with the board report (hardware information). Figure 7-33: Bug report. Viewer page MSC SM2S-IMX8M User Manual 86 / 92...
  • Page 87  Press “Create a zip file” and select the components you want to send (e.g. bootlog, mscio.ini, last kernel logs (dmesg) or the installed hardware). Figure 7-34: Bug report. Content selector MSC SM2S-IMX8M User Manual 87 / 92...
  • Page 88  Press “Save ZIP to a disc” and select the filesystem where to store the zip file. It is recommended to use a USB stick. Figure 7-35: Bug report. Partition selector.  Send the files msc_bug_report_brief.txt and msc_bug_report.zip to MSC: support@msc-technologies.eu MSC SM2S-IMX8M User Manual 88 / 92...

  • Page 89: Hotfixes And Updating Msc-Ldk

    7.3.6 Hotfixes and updating MSC-LDK Typically, twice a year a full MSC-LDK release is issued. A release may contain an updated Yocto or other updated layers as well as new supported boards. For each release an own branch is used (e.g. v1.0.0) which is tagged with the date encoded (e.g. LC984_20150421_V0_4_0, 21st April 2015), too.

  • Page 90: Troubleshooting

    8 Troubleshooting 8.1 Known issues and limitations 8.1.1 Issue 1. Thermal management for i.MX 8M CPU. Source: Hardware Workaround: It is highly recommended to use a suitable cooling concept (for example the heat sink offered by MSC Technologies). The i.MX 8M CPU will tend to consume more power with rising temperature.

  • Page 91: Issue 7. Espi Interface Is Not Available (P57 And P58 Are Crossed)

    8.1.6 Issue 7. ESPI interface is not available (P57 and P58 are crossed) Source: Hardware Solution: Solved with latest hardware release (4 layout revision, DV4). 8.1.7 Issue 8. SDIO_PWR_EN signal is currently not supported in ROM code Source: Hardware Solution: Solved with latest hardware release (4 layout revision, DV4) and latest software relase.

  • Page 92: Support

    8.2 Support For additional help please contact MSC Technical Support: Phone: +49 8165 906-200 https://www.msc-technologies.eu/support/boards.html Email: support@msc-technologies.eu MSC SM2S-IMX8M User Manual 92 / 92...

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