IBM Power System E850C Technical Overview And Introduction page 50

Cache bandwidths
Table 2-7 shows the maximum bandwidth estimates for a single core on the Power E850C
system.
Table 2-7 Power E850C single core bandwidth estimates
Single core
L1 (data) cache
L2 cache
L3 cache
The bandwidth figures for the caches are calculated as follows:
L1 cache: In one clock cycle, two 16-byte load operations and one 16-byte store operation
can be accomplished. The value varies depending on the clock of the core and the formula
is as follows:
– 3.65 GHz Core: (2 x 16 B + 1 x 16 B) x 3.658 GHz = 175.58 GBps
– 3.95 GHz Core: (2 x 16 B + 1 x 16 B) x 3.957 GHz = 189.94 GBps
– 4.22 GHz Core: (2 x 16 B + 1 x 16 B) x 4.223 GHz = 202.70 GBps
L2 cache: In one clock cycle, one 32-byte load operation and one 16-byte store operation
can be accomplished. The value varies depending on the clock of the core and the formula
is as follows:
– 3.65 GHz Core: (1 x 32 B + 1 x 16 B) x 3.658 GHz = 175.58 GBps
– 3.95 GHz Core: (1 x 32 B + 1 x 16 B) x 3.957 GHz = 189.94 GBps
– 4.22 GHz Core: (1 x 32 B + 1 x 16 B) x 4.223 GHz = 202.70 GBps
L3 cache: In one clock cycle, one 32-byte load operation and one 32-byte store operation
can be accomplished. The value varies depending on the clock of the core and the formula
is as follows:
– 3.65 GHz Core: (1 x 32 B + 1 x 32 B) x 3.658 GHz = 234.11 GBps
– 3.95 GHz Core: (1 x 32 B + 1 x 32 B) x 3.957 GHz = 253.25 GBps
– 4.22 GHz Core: (1 x 32 B + 1 x 32 B) x 4.223 GHz = 270.27 GBps
Memory bandwidths
Each processor module in the Power E850C server has two memory controllers, each of
which controls four memory channels, each of which can be connected to a CDIMM. These
high-speed memory channels run at 8 GHz, and can support 2 byte read operations and
1 byte write operation concurrently. This support is independent of the processor clock speed.
So a single processor module can support a memory bandwidth of 8 GHz x 8 channels x (2 x
read byte + 1 x write byte) = 192 GBps. This calculation assumes that all memory CDIMM
slots are populated. If fewer memory CDIMM slots are populated, this figure is lower.
The theoretical maximum memory bandwidth of a server depends on the number of
processor modules installed. These figures are listed in Table 2-8.
Table 2-8 Maximum theoretical memory bandwidths
Processor modules
installed
Maximum theoretical
memory bandwidth
36
IBM Power System E850C: Technical Overview and Introduction
Power E850C Power E850C
One core @ 3.65 GHz One core @ 3.95 GHz
175.58 GBps 189.94 GBps
175.58 GBps 189.94 GBps
234.11 GBps 253.25 GBps
Two processor Three processor
modules installed modules installed
384 GBps 576 GBps
Power E850C
One core @ 4.22 GHz
202.70 GBps
202.70 GBps
270.27 GBps
Four processor
modules installed
768 GBps