Panasonic DMR-EH50GN Service Manual page 49

SPEN SERIAL PORT R/W ENABLE
SPRCLK SERIAL PORT READ CLOCK
SPWCLK SERIAL PORT WRITE CLOCK
SQCK SUB CODE Q CLOCK
SQCX SUB CODE Q DATA READ CLOCK
SRDATA SERIAL DATA
SRMADR SRAM ADDRESS BUS
SRMDT0~7 SRAM DATA BUS 0~7
SS START/STOP
S STAT STATUS
STCLK STREAM DATA CLOCK
STD0~UP STREAM DATA
STENABLE STREAM DATA INPUT ENABLE
STSEL STREAM DATA POLARITY SELECT
STVALID STREAM DATA VALIDITY
SUBC SUB CODE SERIAL
SBCK SUB CODE CLOCK
SUBQ SUB CODE Q DATA
SYSCLK SYSTEM CLOCK
TE TRACKING ERROR
TIBAL BALANCE CONTROL
TID BALANCE OUTPUT 1
TIN BALANCE INPUT
TIP BALANCE INPUT
TIS BALANCE OUTPUT 2
T
TPSN OP AMP INPUT
TPSO OP AMP OUTPUT
TPSP OP AMP INVERTED INPUT
TRCRS TRACK CROSS SIGNAL
TRON TRACKING ON
TRSON TRAVERSE SERVO ON
INITIAL/LOGO
V BLANKING
VBLANK COLLECTOR POWER SUPPLY
VCC VOLTAGE
VCDCONT VIDEO CD CONTROL (TRACKING
V VDD BALANCE)
VFB DRAIN POWER SUPPLY VOLTAGE
VREF VIDEO FEED BACK
VOLTAGE REFERENCE
VSS
SOURCE POWER SUPPLY VOLTAGE
WAIT BUS CYCLE WAIT
WDCK WORD CLOCK
W
WEH WRITE ENABLE HIGH
WSR WORD SELECT RECEIVER
X X TAL
XALE X ADDRESS LATCH ENABLE
XAREQ X AUDIO DATA REQUEST
XCDROM X CD ROM CHIP SELECT
XCS X CHIP SELECT
XCSYNC X COMPOSITE SYNC
XDS X DATA STROBE
XHSYNCO X HORIZONTAL SYNC OUTPUT
XHINT XH INTERRUPT REQUEST
XI X TAL OSCILLATOR INPUT
X
XINT X INTERRUPT
XMW X MEMORY WRITE ENABLE
XO X TAL OSCILLATOR OUTPUT
XRE X READ ENABLE
XSRMCE X SRAM CHIP ENABLE
XSRMOE X SRAM OUTPUT ENABLE
XSRMWE X SRAM WRITE ENABLE
XVCS X V-DEC CHIP SELECT
XVDS X V-DEC CONTROL BUS STROBE
XVSYNCO X VERTICAL SYNC OUTPUT
ABBREVIATIONS