Sharp QD-101MM Service Manual page 16

V
CPU
V
S1
(4.5V)
RESET
signal
V
CC
V
S2
(4.15V)
POWER OFF
DETECTION
signal
When the power is turned on, V
signal is shifted to "High" level at the timing shown in Fig. 10. The reset operation of IC400 is
canceled and executes the program.
When the power is turned off, the power OFF detection signal is shifted to "Low" when V
V drops sharply below V
LCD
On the other hand, Vcpu is backed up by C425 (220mF) so that it can maintain 4.5V for the time
of TW after the trailing edge of the power OFF detection signal. See Fig. 11. (TW is the time
for IC400 to retreat the data to EEPROM.) If V
shifted to "Low", and IC400 starts resetting.
T
PO
Fig.8
Fig.9
, V and V
LCD CC
.
S2
T
PO
rise. If V exceeds V
CPU CPU
drops below V
CPU S1
15
V
(15mV)
T
PO
V
(200mV)
+V , the RESET
S1 HYS1
, the RESET signal level is
HYS1
HYS2
and
CC