HP Vectra XW Optimization Manual page 61

2 Technical Reference
Main Memory
The processor's local data bus is 64 bits wide. All data written to or
read from the memory is transferred on this bus. The memory modules
are accessed by the memory controller through two, parallel 64-bit
data paths. The memory controller connects these two 64-bit data
paths with the processor's bus by interleaving the accesses. This means
that consecutive 64-bit accesses to a memory bank are made to
different modules.
By using interleaving to access the memory banks, the memory
controller actually increases the speed of your system's memory. This is
because of the characteristics of the memory components used.
Main memory uses a type of memory component called Dynamic
Random Access Memory (DRAM). DRAM stores data in a rectangular
array, so that each data item corresponds to an address (location)
which is formed of two parts. These two parts must be sent to the
DRAM in separate clock cycles, which means that the data cannot be
read from or written to the DRAM in the same clock cycle as the
memory controller begins to access it.
With interleaved accesses, the memory controller begins to access both
modules in the pair simultaneously. The time required to access both
memory modules is thus less than twice the time required to access a
single module. The maximum (peak) data transfer rate that your
system's memory can provide is 267 MB/s.
Another advantage of interleaving is that it enables the memory
controller to synchronize its activity with accesses made by the
processor. The Pentium Pro processor frequently uses burst transfers
to read or write entire cache lines in memory. Cache lines are 32 bytes
long, which corresponds to four consecutive data transfers of 64 bits
each.
English 55