HP Vectra XW Optimization Manual page 57

Dedicated Level-Two
Cache Bus
Cache Coherency
The Pentium Pro increases the performance of its level-two cache by
accessing it over a dedicated, 64-bit internal bus. This means that
accesses to the cache will cause no contention with any operations on
the local bus. It also ensures that the level-two cache is able to operate
at the full internal clock speed of the processor.
Level-two cache bus
Level-two cache
One important implication of using cache memories is that duplicate
copies of data exist in different parts of your system. With duplicate
copies of the same data, a mechanism must be used to ensure coherency
between the copies. This is particularly true for dual processor
configurations, where duplications can exist not only between a
processor cache and memory, but also between the caches in the two
processors.
The Pentium Pro's level-two data cache is a copy-back cache, meaning
that if the processor writes data that produces a cache hit, then that
data will be written directly in the level-two cache. The cache will then
copy the data back to memory at a later time. Until the cache copies
the data back to memory, the copy of the data held in memory is no
longer valid.
Processor core
Local
bus
2 Technical Reference
The Intel Pentium Pro Processor
English 51