Data Path Unit (82438Fx) - HP Vectra 510 Technical Reference Manual

Function
PCI master interface
PCI bus arbiter
1.
The Pentium's internal cache has a 32-byte line size, which is four times the width of the Pentium's
host data bus. Burst reads and writes by the Pentium involve a full cache line, and so require four
back-to-back cycles to complete. The first cycle in each burst of four always requires more time to
complete than the three subsequent cycles. This is because the first cycle includes the addressing
phase and precharge timing (for memory).

Data Path Unit (82438FX)

The 82438FX component contains a 64-bit data path between the host bus
and main memory. A 4
memory.
This buffer is used for:
• writes from processor to main memory
• level-two cache write back cycles
• transfers from PCI to main memory.
Provides for programmable PCI bus memory regions in
memory address map
Supports PCI bus burst cycles for 64-bit and 32-bit misaligned
Pentium reads and writes
Optional posting of PCI memory and I/O writes
Optional buffering of PCI memory writes
Optional read-ahead for processor to PCI accesses
Supports PCI bus arbitration for up to four masters
Supports rotating priority scheme
×
64-bit deep buffer provides 3-1-1-1 writes to main
1 HP Vectra 500 Series
Principal Components and Features
Features
13