Table of Contents
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Pin
Port
No.
105 A16
Address bus of FLASH
ROM
106 DVSS7 GND
107 A17
Address bus of FLASH
ROM
108 A18
109 A19
110 A20
111 CVSS9 GND
112 DVDD5 I/O system (3.3V) power
supply
113 D6
Data bus of FLASH ROM
114 D7
115 D8
116 D9
117 D10
118 D11
Data bus of FLASH ROM
119 D12
120 STAT
Status signal input
121 D13
Data path of FLASH ROM
122 D14
123 D15
124 SQCK
SOCK clock output(To
Servo DPS)
125 CVDD6 CORE CPU system (1.6V)
power supply
126 CVSS10 GND
127
-
128 DVSS8 I/O system (3.3V) power
supply
129
-
130 DVDD6 I/O system (3.3V) power
supply
131 A0
Address bus of FLASH
ROM
132 A1
133 A2
134 A3
135 /RST
Reset signal output(To
Servo DSP)
136 A4
Address bus of FLASH
ROM
137 A5
138 A6
139 A7
140 A8
141 A9
Descriptions
-
-
I/O (V)
O
0
-
0
O
3.3
O
0
O
0
O
0
-
0
-
3.3
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I
0.4
I/O
0
I/O
0
I/O
0
O
3.2
-
1.6
-
0
-
-
-
0
-
-
-
3.3
O
0
O
0
O
3.3
O
3.3
O
3.3
O
3.3
O
0
O
3.3
O
3.3
O
0
O
3.3
15
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- Wiring Connection
- Wiring Diagram
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