Table of Contents
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Pin
Port
No.
69 SW1
Mechanics deck SW1 input
70 CVSS7 GND
71 MCLK
Clock output (To Servo
DSP)
72 DVSS4 GND
73 MLD
Command load signal
output (To Servo DSP)
74 MDATA Command data output (To
Servo DSP)
75 DVDD4 I/O system (3.3V) power
supply
76 DVSS5 GND
77
-
Clock mode setting (L
fixation)
78
-
Clock mode setting (H
fixation)
79
-
Clock mode setting (L
fixation)
80
-
81 SW2
Mechanics deck SW2 input
82
-
83
-
84
-
85
-
86
-
87
-
88
-
89
-
90 CVSS8 GND
91 CVDD5 CORE CPU system (1.6V)
power supply
92 (GND)
GND
93 DVSS6 GND
94
-
95 CLKENA Oscillation output Cainabl
signal
96 ×1
Crystal Connection
97 ×2
Crystal Connection
98 (VDD)
Reset signal input
99 D0
Data base of FLASH ROM
100 D1
101 D2
102 D3
103 D4
104 D5
Descriptions
-
-
-
-
-
-
-
-
-
-
I/O (V)
I
0
-
0
O
3.3
-
0
I
3.3
O
3.3
-
3.3
-
0
I
0
I
3.3
I
-
-
-
I
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.3
-
0
I
1.6
-
0
-
-
O
3.3
O
0
I
0
I
1
I/O 3.4
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
14
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- Wiring Diagram
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