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Schematic Diagrams
s
m
a
r
Sheet 19 of 41
g
i a
POWERGOOD/
D
TPM
i c
t
a
m
e
h
c
S
.
B
B - 20 POWERGOOD/ TPM
POWERGOOD/ TPM
33
1 .1 V_ P W RG D
16
SY S_ RS T#
R 7 7 5
0_ 0 4
34
1 .8 V_ P W RG D
R 7 7 6
* 0 _ 0 4
3 2 ,35
D DR 1.5 V_ P W R GD
1 6 ,2 6, 27 ,3 0
SUS B#
ON
TPM 1.2
1 5 ,2 7
L P C_ A D0
1 5 ,2 7
L P C_ A D1
1 5 ,2 7
L P C_ A D2
1 5 ,2 7
L P C_ A D3
1 5
PC L K_T PM
15 ,2 7
LP C_ F RAM E #
1 5 ,23 ,2 4 ,26 ,2 7
BUF _ PL T _R ST #
15 ,2 7
S E R I R Q
1 5
PCI_ C LK R UN #
1 6
S4 _ ST ATE #
Asserte d beforeentering S3
LPCreset t iming :
LPC PD# inactiv e to LRST# inactive32~96us
TPM_PP
TPM_BADD
3 .3 V
4
U2 2 B
1
7 4 LVC 0 8P W
4
6
5
7
3 5
P W RG D_ VC ORE
3 .3 V
3 .3 V
3 .3 V
U2 2 A
4
1
4
7 4 LVC 0 8P W
U 22 D
1
9
7 4 LVC 0 8PW
4
1
1 2
1
11
1 0
3
1 3
2
7
7
7
U 5 0
C8 7 6
C 8 77
2 6
10
R 8 14
* 0 _ 0 4
L A D0
V DD 1
2 3
19
R 8 16
* 0 _ 0 4
*0 .1 u _1 6 V_ Y5 V _ 04
2 0
L A D1
V DD 2
24
R 8 17
* 0 _ 0 4
*0 .1 u _1 6 V _ Y 5 V_ 04
L A D2
V DD 3
1 7
R 8 15
* 0 _ 0 4
L A D3
2 1
TPM
3 .3 VS
L CL K
2 2
5
R 8 18
* 0 _ 0 4
1 6
L F RAM E #
VS B
R 8 19
* 0 _ 0 4
L RESE T#
2 7
R 8 20
* 0 _ 0 4
C8 8 0
1 5
SE R IRQ
C LKR UN #
*0 .1 u _1 6 V_ Y5 V _ 04
2 8
6
T P M3 0 04
L P CPD #
G P I O
2
T P M3 0 05
9
GP IO 2
T PM _ BAD D
T E ST B I/B AD D
13
XTALI
7
X T A LI
T PM _ PP
PP
X12
* 3 2.7 6 8 KHz
14
4
1
XTALO
XT AL O
T P M3 0 0 1
1
3
2
3
N C_ 1
4
T P M3 0 0 2
N C_ 2
GN D_ 1
T P M3 0 0 3
1 2
11
X13
* 3 2.7 6 8 KHz
N C_ 3
GN D_ 2
18
4
1
GN D_ 3
8
25
3
2
T E ST I
GN D_ 4
C8 81
C8 8 2
* SL B 96 3 5 TT
*1 8p _ 5 0V_ N PO_ 0 4
*1 8 p_ 5 0 V _N P O_ 0 4
PCL K_ TP M
R 8 2 1
* 3 3 _ 04
C 8 83
HI:ACCESS
3 .3 VS
LOW: N ORMAL( Internal PD)
T PM_ PP
R 8 2 2
* 1 0 K _ 04
HI:4E/4FH
T PM_ BAD D
R 8 2 3
* 1 0 K _ 04
LOW: 2E/ 2FH
R 8 2 4
* 1 0 K _ 04
3 .3 V
R7 74
U2 2 C
10 K_ 0 4
SB _ P W RO K
74 L VC0 8 P W
R 3 6 4
0 _0 4
SB _ P W R GD
8
SY S _PW R OK
R 3 6 5
0 _0 4
AL L _ SYS _ PW R GD 2 0 ,2 7
C 84 1
R3 6 7
1 u_ 6 .3 V_Y 5 V _0 4
*1 0 K_ 04
3 .3 VS
C8 7 8
C 87 9
*0 .1 u_ 1 6 V_Y 5 V _0 4
* 1u _ 1 6V_ X5 R_ 06
*1 0 p _ 5 0 V_ 0 4
16
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