Robson Ddr3 Mem Ch-B - Clevo W241BU Service Manual

Robson DDR3 MEM CH-B

VREF C_U 11 M8
VREF D_U 11 H1
M A A 0 N3
M A A 1 P7
M A A 2 P3
N2
M A A 3
9 , 1 3 MAA[1 3..0]
P8
M A A 4
P2
M A A 0 M A A 5
R8
M A A 1 M A A 6
R2
M A A 2 M A A 7
T8
M A A 3 M A A 8
R3
M A A 4 M A A 9
M A A 5 MAA1 0 L7
M A A 6 MAA1 1 R7
M A A 7 MAA1 2 N7
M A A 8 MAA1 3 T3
M A A 9 T7
MAA1 0 M7
MAA1 1
MAA1 2
MAA13 M2
9 ,13 A_BA0
N8
9 ,13 A_BA1
M3
9 ,13 A_BA2
9 DQ MA1 _ [3 ..0]
DQMA1 _0
DQMA1 _1
DQMA1 _2 J7
9 CLKA1
DQMA1 _3 K7
9 CLKA1 #
K9
9 CKEA1
9 QSA1 _ [ 3 ..0]
K1
QSA1_ 0 ODT A1
L2
Q S A 1 _ 1
9 CSA 1b _ 0 J3
QSA1_ 2
9 RASA1 # K3
QSA1_ 3
9 CASA1 #
L3
9 W EA1 #
QSA 1_ 0 B
9 QSA1_ 0B
QSA 1_ 1 B QSA1 _0 F 3
9 QSA1_ 1B
Q S A 1 _ 2B QSA1 _1 C7
9 QSA1_ 2B
QSA 1_ 3 B
9 QSA1_ 3B
DQ MA1_ 0 E7
DQ MA1 _ 1 D3
QSA1 _0 B G3
QSA1 _1 B B7
T2
9 ,13 MEM_ RST
O D T A 1
9 O DTA1
L8
R20 5
*24 3_ 1% _0 4
9 C LKA1
R23 6
*56 _0 4
J1
L1
R23 7 C41 1 J9
*56 _0 4 *0 . 0 1u _ 16 V_ X7 R_ 04 L9
9 C LKA1#
COMPONENTS SHOWN ARE EXAMPLES ONL Y
AND NOT NECESSARILY QUAL IFIED
U1 1 U1 2
DQA1 _[1 5..8] 9
E3 DQA1 _0 VREF C_U 12 M8
V R E F C A DQL0 VREF CA
F7 DQA1 _2 VREF D_U 12 H1
V R E F D Q DQL1 VREF DQ
F2 DQA1 _7
DQL2
F8 D QA1 _ 3 M A A 0 N3
A0 DQL3 H3 DQA1 _6 M A A 1 P7 A0
A1 DQL4 H8 DQA1 _4 M A A 2 P3 A1
A2 DQL5 G2 N2 A2
DQA1 _5 M A A 3
A3 DQL6 H7 P8 A3
D QA1 _ 1 M A A 4
A4 DQL7 P2 A4
M A A 5
A5 R8 A5
M A A 6
DQA1 _[7 .. 0 ] 9
A6 D7 R2 A6
D QA1 _ 11 M A A 7
A7 DQU0 C3 T8 A7
D QA1 _ 12 M A A 8
A8 DQU1 C8 R3 A8
D QA1 _ 9 M A A 9
A9 DQU2 A9
C2 D QA1 _ 8 MAA1 0 L7
A1 0/AP DQU3 A1 0/AP
A7 D QA 1 _ 14 MAA1 1 R7
A1 1 DQU4 A1 1
A2 D QA1 _ 15 MAA1 2 N7
A1 2/BC DQU5 A1 2/BC
B8 D QA1 _ 10 MAA13 T3
A1 3 DQU6 A1 3
A3 D QA1 _ 13 T7
A1 4 DQU7 A1 4
M7
A1 5 A1 5
MVDDQ
B2 M2
BA0 VDD# B2 9 ,13 A_BA0 BA0
D9 N8
BA1 VD D#D9 9 ,13 A_BA1 BA1
G7 M3
BA2 VD D#G7 9 ,13 A_BA2 BA2
K2
VDD# K2
K8
VDD# K8
N1
VD D#N1 N9 J7
9 CLKA1
C K VD D#N9 R1 K7 C K
9 CLKA1 #
C K VD D#R1 R9 K9 C K
9 CKEA1
C KE VD D#R9 C KE
MVDDQ
A1 K1
ODT A1
O DT VDDQ# A1 A8 L2 O DT VDDQ#A1
C S VDDQ# A8 C1 9 CSA1 b_ 0 J3 C S VDDQ#A8
R AS VDD Q#C1 C9 9 RASA1 # K3 R AS VDDQ #C1
C AS VDD Q#C9 9 CASA1 # C AS VDDQ #C9
D2 L3
W E VDD Q#D2 9 WEA1 # W E VDDQ #D2
E9
VDDQ# E9 VDDQ#E9
F1
VDDQ# F1 VDDQ#F 1
H2 QSA1_ 2 F 3
D Q S L VDD Q#H2 D QSL VDDQ #H2
H9 QSA1_ 3 C7
D Q S U VDD Q#H9 D QSU VDDQ #H9
A9 DQMA1 _2 E7
D ML VSS# A9 D ML
B3 DQMA1 _3 D3
D MU VSS# B3 D MU
E1
VSS# E1
G8
VSS#G8
J2 QSA1_ 2B G3
D Q S L VSS# J2 D QSL
J8 QSA1_ 3B B7
D Q S U VSS# J8 M1 D QSU
VSS#M1 M9
VSS#M9 P1
VSS# P1 P9 T2
9 ,13 MEM_ RST
R ESET VSS# P9 T1 R ESET
VSS# T1 T9 L8
Z Q VSS# T9 Z Q
R20 6
B1
*24 3_ 1% _0 4
VSSQ# B1 V S S Q # B 1
B9
VSSQ# B9 V S S Q # B 9
D1
VSSQ#D1 VSSQ #D1
D8
VSSQ#D8 VSSQ #D8
E2
VSSQ# E2 V S S Q # E 2
E8 J1
N C#J 1 VSSQ# E8 N C#J 1 V S S Q # E 8
F9 L1
N C#L 1 VSSQ# F9 N C#L 1 VSSQ#F 9
G1 J9
N C#J 9 VSSQ#G1 N C#J 9 VSSQ #G1
G9 L9
N C#L 9 VSSQ#G9 N C#L 9 VSSQ #G9
1 00 -BAL L 10 0 - B AL L
SDRAM DDR3 S D R A M D D R 3
*K4 W1 G16 4 6G-BC1 1 *K4W 1 G16 46 G-BC11
CHANNEL A: 64M X 16 b it X8 DDR3 (RANK1)
DQA1 _[2 3..16 ] 9
E3 DQA1 _2 1
D QL0
F 7 DQA1 _2 2
D QL1
F 2 DQA1 _1 6
D QL2
F 8 DQA1 _2 3
D QL3 H 3 DQA1 _1 8
D QL4 H 8 DQA1 _2 0
D QL5 G 2
DQA1 _1 9
D QL6 H 7
D Q A 1 _1 7
D QL7
MVDDQ
DQA1 _[3 1..24 ] 9
D 7
DQA1 _2 8 C3 9 1 C39 2 C39 3 C3 94 C3 95
DQU0 C 3
DQA1 _2 6
DQU1 C 8 4 4 4
D Q A 1 _3 1 4 4
0 0 0 0 0
DQU2 _ _
C 2 D Q A 1 _2 4 _ _ _
R R
R R R
DQU3 5 5 5 5
A7 DQA1 _2 9 5
X X X X X
DQU4 _ _ _
A2 DQA1 _2 5 _ _
V V V
DQU5 3 V V
B8 DQA1 _3 0 . 3 3 3 3
DQU6 . 6 . 6 . 6 .
A3 DQA1 _2 7 6
_ 6
DQU7 _ u _ u _ u _
u
1 u
1 1 1 1
* * * * *
MVDDQ
MVDDQ
B2
VDD#B2
D 9
C4 1 2 C41 3 C41 4 C4 15 C4 16
VDD #D9
G 7
VDD #G7 4 4 4
K2 4 4
0 0 0 0 0
_ _
VDD#K2 _ _ _
K8 R R
R R R
VDD#K8 5 5 5 5
N 1 5
X X X X X
_ _ _
VDD #N1 N 9 _ _
V V V
3 V V
VDD #N9 R 1 . 3 3 3 3
. 6 . 6 . 6 .
VDD #R1 R 9 6
_ 6
_ u _ u _ u _
u
VDD #R9 1 u
MVDDQ 1 1 1 1
* * * * *
A1
MVDDQ MVDDQ
A8
C 1
C4 3 4 C43 5 C43 6 C4 37
C 9
6 6 6 6
D 2 0 0
0 0
_ _ _ _
E9
R R R R
5
F 1 5 5 5
X X
X X
H 2 V _ _ _ _
H 9 V V V
3 3
6 . 3 3 . .
6 .
6 6
u _ _ _
u _
u u
0 0 0
1 0
A9 1 1 1
* * * *
V S S # A 9
B3
V S S # B 3
E1
V S S # E 1
G 8
VSS#G8
J 2
VSS# J2
J 8
VSS# J8 M 1
MVDDQ MVDDQ
VSS#M1 M 9
VSS#M9 P1
V S S # P 1 P9
V S S # P 9 T 1
R22 4
VSS# T1 T 9
*4.9 9K_ 1% _0 4
VSS# T9
VREF C_ U11 VREF C_ U11
B1
B9
D 1 R23 2 C3 87
D 8 *0 .1u _1 0V_ X5 R_0 4
E2 *4.9 9K_ 1% _0 4
E8
F 9
G 1
G 9
MVDDQ MVDDQ
R22 6
*4 . 9 9 K_ 1% _0 4
VR EF C_ U12
R23 4 C3 89
*0 .1u _1 0V_ X5 R_0 4
*4 . 9 9 K_ 1% _0 4
Schematic Diagrams
Sheet 14 of 41
C3 96 C39 7 C39 8 C3 99 C4 00
4 4 4 4 4
0 0 0
0 0
_ _ _ _ _
Robso n DDR3 MEM
R R R R
5 R 5
5 5 5
X X X
X X
V _ _ _ _ _
V V V V
0 0 0
1 0 0
1 1 1 1
u _ _ _
u _ u _ CH-B
u u
1 1 1
0 . 1 1 . .
0 . 0 .
0 0
* * * * *
C4 17 C41 8 C41 9 C4 20 C4 21
4 4 4 4 4
0 0 0
0 0
_ _ _ _ _
R R R R
5 R 5
5 5 5
X X X
X X
V _ _ _ _ _
V V V V
0 0 0
1 0 0
1 1 1 1
u _ _ _
u _ u _
u u
1 1 1
0 . 1 1 . .
0 . 0 .
0 0
* * * * *
C83 8
+
* 22 0u _4 V_V_A
R2 25
* 4.99 K _1 %_ 04
VREF D_U1 1 VREF D_U1 1
R2 33 C38 8
*0.1 u_ 10 V_X5R_ 04
* 4.99 K _1 %_ 04
R2 2 7
* 4.9 9K_1 %_ 04
VREF D_U1 2
R2 3 5 C39 0
*0.1 u_ 10 V_X5R_ 04
* 4.9 9K_1 %_ 04
Robson DDR3 MEM CH-B B - 15
B
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