Compaq 6000 Supplementary Manual page 11

ECG066/1198
T B
ECHNOLOGY RIEF
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Crossbar Switch Architecture
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A crossbar switch architecture provides multiple, independent paths to system memory. As
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. . Figure 8 illustrates, individual paths can be established to memory from each processor or I/O
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bus. Thus, a crossbar switch can avoid contention of multiple memory requests on a given bus.
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This style of crossbar switch is used in the Sun Microsystems Unified Port Architecture (UPA)
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and the Compaq TriFlex architectures.
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CPU
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Figure 8. Crossbar switch architecture.
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The Sun UPA provides a peak memory bandwidth of 1.2 GB/s in its full implementation. In
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. . other Sun implementations, however, memory bandwidth is half that or less. The actual memory
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throughput of a Sun system with UPA architecture will be limited by the same DRAM constraints
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. . identified earlier in the section "Dual Memory Buses."
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By allowing separate paths to system memory, this style of crossbar switch can improve
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performance of both I/O traffic and processor cycles. A crossbar switch for a single processor
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bus, memory bus, and I/O bus can be implemented cost effectively. However, a crossbar switch is
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an expensive solution in a system with several buses. The reason is that all the buses must go into
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a single chip that has sufficient pins for each bus. This requires a large and expensive chip when
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several buses are implemented in the crossbar switch. A crossbar switch supporting the processor
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. . bus, two PCI buses, and two memory buses is not cost effective with today's silicon technology.
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Compaq chose not to use a crossbar switch because a better architectural solution was possible for
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the following reasons. First, the Pentium Pro processor bus is capable of running up to eight
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transactions simultaneously. Since the I/O cycle can be run simultaneously with processor cycles
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on the shared processor bus, independent paths to memory are not as critical. Furthermore, the
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I/O cache significantly reduces the amount of bandwidth required by each PCI bus on the
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processor bus. Second, having dual-peer PCI buses and two memory buses can produce
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significant performance increases. The new architecture using dual-peer PCI buses and dual
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memory controllers on a shared processor bus gives better performance than a crossbar switch
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. . with a single memory controller and a single PCI bus. Moreover, the higher performance comes
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at a price point well below that of a crossbar switch with dual memory controllers and dual PCI
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buses.
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11
(cont.)
Crossbar
Switch
Memory
Controller
PCI PCI Slots and
other Devices
Controller