Clevo W270CZQ Service Manual page 49

Schematic Diagrams
Processor 2/7
PU/PD for JTAG signals
VTT_CPU
Sheet 3 of 44
Processor 2/7
0627 D02
[11,17,23]
B - 4 Processor 2/7
Ivy/Sandy Bridge Processor 2/7
R416 *51_04 XDP_TMS
R108 *51_04 XDP_TDI_R
R109 *51_04 XDP_PREQ#
R415 *51_04 XDP_TDO_R
XDP_TCLK
R414 *51_04
XDP_TRST#
R95 51_04
H_SNB_IVB#
[18] H_SNB_IVB#
3.3VS
R407 *1K_04 XDP_DBR_R
H_CATERR#
H_PECI_R
R411 *10mil_04
[18,28] H_PECI
H_PROCHOT# R405 56_1%_04 H_PROCHOT#_D
[37] H_PROCHOT#
If PROCHOT# is not used, then it must
be terminated with a 68-£[ +-5%
pull-up resistor to 1.05VS_VTT .
H_THRMTRIP#_R
R417 *10mil_04
[18] H_THRMTRIP#
R419 *10mil_04 PM_SYNC_R
[15] H_PM_SYNC
H_CPUPWRGD_R
R418 *10mil_04
[18] H_CPUPWRGD
PMSYS_PWRGD_BUF R60 130_1%_04 VDDPWRGOOD_R
Buffered reset to CPU
VTT_CPU
BUF_CPU_RST#
R105 *75_1%_04 R104 *43_1%_04
6
3.3VS
D
Q36A
R530 *10K_04 2 G *MTDK5S6R
S
3 1
D
5 G Q36B
S *MTDK5S6R
4
R112 1.5K_1%_04
PLT_RST#
[28]
R531 C96 R106
*100K_04 *68p_50V_NPO_04 750_1%_04
CAD Note: Capacitor
need to be placed
close to buffer output pin
( CLK,MISC,JTAG )
U34B
J3
BCLK
F49 H2
PROC_SELECT# BCLK#
C57
PROC_DETECT# AG3
DPLL_REF_CLK
AG1
DPLL_REF_CLK#
C49
CATERR#
A48 AT30 CPUDRAMRST#
PECI SM_DRAMRST#
C45 BF44
SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
BE43 SM_RCOMP_1
SM_RCOMP[1]
BG43 SM_RCOMP_2
SM_RCOMP[2]
D45
THERMTRIP#
N53 XDP_PRDY #
PRDY# N55
XDP_PREQ#
PREQ#
L56 XDP_TCLK
TCK
L55 XDP_TMS
TMS
C48 J58 XDP_TRST#
PM_SY NC TRST#
M60
XDP_TDI_R
TDI
L59 XDP_TDO_R
TDO
B46
UNCOREPWRGOOD
K58
XDP_DBR_R
DBR#
BE45
SM_DRAMPWROK
G58 XDP_BPM0_R
BPM#[0]
E55 XDP_BPM1_R
BPM#[1] E59
XDP_BPM2_R
D44 BPM#[2] G55
XDP_BPM3_R
RESET# BPM#[3]
G59
XDP_BPM4_R
BPM#[4]
H60 XDP_BPM5_R
BPM#[5]
J59 XDP_BPM6_R
BPM#[6]
J61 XDP_BPM7_R
BPM#[7]
P31X24_1023B_01B
H_PROCHOT#
Q14
G
H_PROCHOT_EC
2SK3018S3 C515
47p_50V_NPO_04
R91 *100K_04
[2,6,11,13,14,15,17,18,19,20,22,23,26,28,32,34,35,36]
[9,10,11,12,13,14,15,16,17,18,19,20,23,24,25,28,29,30,31,32,37]
Processor Pullups/Pull downs
H_PROCHOT# R410 62_04
H_CPUPWRGD_R R412 10K_04
C585 *0.1u_10V_X7R_04
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
CLK_EXP_P [14]
CLK_EXP_N [14]
SM_RCOMP_0 R413 140_1%_04
SM_RCOMP_1 R382 25.5_1%_04
SM_RCOMP_2
R381 200_1%_04
S3 circuit:- DRAM PWRGOOD logic
3.3V 1.5V_CPU
R73
*200_1%_04
D20
1
A
[15] PM_DRAM_PWRGD
3
C
2 A
[15,34] 1.8VS_PWRGD
*BAT54AS3
R59 *10mil_04
G
[32,34,35] SUSB
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R47 *0_04
R45
1K_04
Q8
2SK3018S3
CPUDRAMRST# S D
R48 1K_04
DDR3_DRAMRST# [9,10]
R46
DRAMRST_CNTRL [14]
C22
0.047u_10V_X7R_04
[2,5,18,19,20,35,36] VTT_CPU
[5,6,32] 1.5V_CPU
[6,9,10,20,32,34] 1.5V
3.3V
3.3VS
VTT_CPU
R57
10K_04
PMSY S_PWRGD_BUF
R58
*39_04
Q10
*2SK3018S3