VersaLogic VL-EPME-30ECP Hardware Reference Manual page 55

Table of Contents

SPIDATA0 (READ/WRITE) C8Ah

MSbit

SPIDATA1 (READ/WRITE) C8Bh

MSbit

SPIDATA2 (READ/WRITE) C8Ch

MSbit

SPIDATA3 (READ/WRITE) C8Dh

MSbit

SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this register

initiates the SPI clock and, if the MAN_SS bit = 0, also asserts a slave select to begin an SPI bus

transaction. Increasing frame sizes from 8-bit uses the lowest address for the least significant byte

of the SPI data word; for example, the LSB of a 24-bit frame would be SPIDATA1. Data is sent

according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSbit of SPIDATA3 is sent first,

and received data will be shifted into the LSbit of the selected frame size set in the SPILEN field.

When LSBIT_1ST = 1, the LSbit of the selected frame size is sent first, and the received data will

be shifted into the MSbit of SPIDATA3.

Data returning from the SPI target will normally have its most significant data in the SPIDATA3

case, the most significant byte of an 8-bit transaction will be located in SPIDATA0, a 16-bit

transaction's most significant byte will be located in SPIDATA1, and a 24-bit transaction's most

significant byte will be located in SPIDATA2

Bengal (VL-EPMe-30) Reference Manual

Interfaces and Connectors

LSbit

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