TYAN S8020 Manual page 113

TpProcCpuOptimizedBootEnd
TpProcCpuApobCcxEdcInitStart
TpProcCpuApobCcxEdcInitEnd
TpProcCpuInitAfterReplayBufferStart
TpProcCpuInitAfterReplayBufferEnd
// Topology test points
TpProcTopologyEntry
TpProcTopologyDone
// Extended memory test point
TpProcMemSendMRS2
TpProcMemSendMRS3
TpProcMemSendMRS1
TpProcMemSendMRS0
TpProcMemContinPatternGenRead
TpProcMemContinPatternGenWrite
TpProcMem2dRdDqsTraining
TpProcMemBefore2dTrainExtVrefCh
ange
TpProcMemAfter2dTrainExtVrefChan
ge
TpProcMemConfigureDCTForGenera
l
TpProcMemProcConfigureDCTForTr
aining
TpProcMemConfigureDCTNonExplici
tSeq
TpProcMemSynchronizeChannels
TpProcMemC6StorageAllocation
TpProcMemLvDdr4
boot init
= 0xE056, ///< Exit point CPU Optimized
boot
init
= 0xE057, ///< Entry point CPU APOB
EDC
info init
= 0xE058, ///< Exit point CPU APOB EDC
info init
= 0xE059, ///< Entry point CPU init after
replay buffer
= 0xE05A, ///< Exit point CPU init after
replay buffer
= 0xE071, ///< ProcTopologyEntry
= 0xE07C, ///< ProcTopologyDone
= 0xE080, ///< ProcMemSendMRS2
= 0xE081, ///< Sedding MRS3
= 0xE082, ///< Sending MRS1
= 0xE083, ///< Sending MRS0
= 0xE084, ///< Continuous Pattern Read
= 0xE085, ///< Continuous Pattern Write
= 0xE086, ///< Mem: 2d RdDqs Training
begin
= 0xE087, ///< Mem: Before optional
callout to platform BIOS to change
External Vref during 2d Training
= 0xE088, ///< Mem: After optional callout
to platform BIOS to change External Vref
during 2d Training
= 0xE089, ///< Configure DCT For
General use begin
= 0xE08A, ///< Configure DCT For
training begin
= 0xE08B, ///< Configure DCT For Non-
Explicit
= 0xE08C, ///< Configure to Sync
channels
= 0xE08D, ///< Allocate C6 Storage
= 0xE08E, ///< Before LV DDR4
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