Nemic-Lambda TDK-Lambda Genesys GEN6-100 Manual page 65

Refer to Tables 7-10 to 7-13 for details of the Enable and Event registers.
1.Fault Enable Register
The Fault Enable Register is set to the enable faults SRQs.
Table 7-10: Fault Enable Register
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over Temperature
3 Foldback
4 Over Voltage
5 Shut Off
6 Output Off
7(MSB) Enable
2.Fault Event Register
The Fault Event will set a bit if a condition occurs and it is enabled. The register is cleared when
FEVE?, CLS or RST commands are received.
Table 7-11: Fault Event Register
Event
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over Temperature
3 Foldback
4 Over Voltage
5 Shut Off
6 Output Off
7(MSB) Enable
Fault symbol
Bit Set condition
SPARE
AC
OTP
User command:
"FENA nn" where
FOLD
nn is hexadecimal
OVP
SO
OFF
ENA
Fault symbol
Bit Set condition
SPARE
Fault condition
AC
occurs and it is
enabled.
OTP
The fault can set
a bit, but when
FOLD
the fault clears
the bit remains
OVP
set.
SO
OFF
ENA
59
Bit reset condition
User command: "FENA nn"
where nn is hexadecimal (if
nn="00", no fault SRQs will
be generated).
Bit reset condition
Entire Event Register is
cleared when user sends
"FEVE?" command to read
the register.
"CLS" and power-up also
clear the Fault Event
Register. (The Fault Event
Register is not cleared by
RST)