Gate-Source Driver Voltage - Texas Instruments UCC5390SCD User Manual

Power Up, Capturing Waveforms, and Power Down
1. Expand the horizontal scale of oscilloscope from 2 µs/div to 10 ns/div, and verify rise and fall time of
the driver board indicating high output current capability of UCC5390SCD driver ICs
Figure 8).
2. Return to the initial horizontal scale 2 µs/div.
3. Set the electronic load to 0-A current.
4. Enable the high voltage power supply and gradually increase in voltage from 0 V to 800 V. The
waveforms should look similar to
5. Explore the rising and falling edges of the phase node (Vds of lower FET) by changing horizontal scale
to 100 ns/div. as it is shown in
soft switching with minimum ringing.
6. Return to the initial horizontal scale 2 µs/div.
7. Gradually increase the load current up to 1.0 A. The waveforms should look similar to
Explore the rising and falling edges of the phase node (Vds of lower FET) by changing horizontal scale
to 10 ns/div for rising edge and 100 ns/div. for falling edge as it is shown in
8. Verify that at load 1.0 A, the rising edge is under hard switching with increased ringing versus the
falling edge that is under soft switching.
9. Return to the initial horizontal scale 2 µs/div.
10. Gradually reduce the voltage of the high voltage supply down to 0 V.
11. Disable channel A and channel B of function generator.
12
UCC5390SCD With Isolated Bias Supply
Figure 6. Gate-Source Driver Voltage
Figure 9.
Figure 10 and Figure
Copyright © 2017–2018, Texas Instruments Incorporated
11. Verify that at 0-A load both edges are under
Figure 13
SLLU282A – December 2017 – Revised February 2018
Submit Documentation Feedback
www.ti.com
(Figure 7 and
Figure 9.
and Figure 14.