User Manuals: Ingenic XBurst 2 CPU Core Low Power

Manuals and User Guides for Ingenic XBurst 2 CPU Core Low Power. We have 1 Ingenic XBurst 2 CPU Core Low Power manual available for free PDF download: Programming Manual

Ingenic XBurst 2 CPU Core Programming Manual (143 pages)

Brand: Ingenic | Category: Computer Hardware | Size: 1 MB

Table of Contents
3
Overview
7
Features of Xburst®2 CPU for X2000
7
Operating Modes
8
Cp0
10
CP0 Register Summary
10
CP0 Registers Grouped by Function
10
CP0 Registers Grouped by Number
12
CP0 Register Formats
14
CP0 Register Field Types
14
CP0 Register Descriptions
15
CPU Configuration and Status Registers
15
TLB Management Registers
31
Exception Control Registers
40
Timer Registers
45
Cache Management Registers
46
Thread Context and Shadow Control Registers
47
CPU Performance Monitor Registers
48
Debug Registers
50
User Mode Support Registers
56
Kernel Mode Scratch Registers
58
Exceptions and Interrupts
60
Exception Priority
60
Exception Vector Locations
61
Exception Handling Process
62
Enter Exception Handler Routine
62
Return from Exception Handler Routine
62
Exception Categories
63
Memory Management Unit
65
Overview
65
Virtual Memory Space
66
User Mode
66
Kernel Mode
67
Tlb
69
Instruction Micro TLB
69
Data Micro TLB
69
Variable Page Size TLB (VTLB)
69
Fixed Page Size TLB (FTLB)
72
Filling JTLB Entry
73
Virtual to Physical Address Translation
74
Caches
75
L1-Cache
75
Cache Coherency Attribute
75
Cache Relative CP0 Registers
76
Cache Operation Relative Instructions
76
PREF/PREFX Instruction
79
SYNC Instruction
80
L2-Cache
81
Initialize Core State
82
Initialized Core State by Hardware
82
Coprocessor 0 State
82
TLB Initialization
82
Cache Initialization
82
Initialized Core State by Software
82
General Purpose Registers Initialization
82
Ccu
83
Overview
83
Register Description
84
Cores Sleep Control Register
85
Core Sleep Status Register
86
Core Software Reset Register
87
Memory Subsystem Control Register
88
Memory Subsystem Implementation Register
89
CPU Configuration Register
90
Peripheral IRQ Pending Register
91
Peripheral IRQ Mask Register
91
Mailbox IRQ Pending Register
92
Mailbox IRQ Mask Register
92
OST IRQ Pending Register
93
OST IRQ Mask Register
93
Debug Interrupt Pending Register
94
Debug Interrupt Mask Register
94
Reset Entry Register
95
Mailbox Register<N
95
CCU Spin Lock Register
96
CCU Spin Atomic Register
96
Global Interrupt Mask Register
97
CPU Feature Configuration Register
98
Bus Exception Control Register
99
Usage
100
The Configuration of CCU
100
EJTAG Debug Support
101
Overview
101
Detecting Debug Mode
102
Ways of Entering Debug Mode
102
Exiting Debug Mode
102
Hardware Breakpoints
102
Instruction Breakpoints
103
Data Breakpoints
103
Overview of Instruction Breakpoint Registers
103
Overview of Data Breakpoint Registers
103
Conditions for Matching Breakpoints
104
Conditions for Matching Instruction Breakpoints
104
Conditions for Matching Data Breakpoints
104
SIMD Load/Store Handling
105
Debug Exceptions from Breakpoints
105
Debug Exception by Instruction Breakpoint
106
Debug Exception by Data Breakpoint
106
Breakpoint Used as Triggerpoint
106
Test Access Port (TAP)
106
EJTAG Internal and External Interfaces
107
Test Access Port Operation
107
Test Access Port (TAP) Instructions
111
TAP Processor Accesses
113
EJTAG Registers
115
General Purpose Control and Status
115
Instruction Breakpoint Registers
116
Data Breakpoint Registers
119
EJTAG TAP Registers
124
Debug Exception
132
Debug Exception Priorities
132
Debug Exception Vector Location
133
General Debug Exception Processing
133
Debug Single Step Exception
134
Debug Interrupt Exception
135
Debug Instruction Break Exception
135
Debug Breakpoint Exception
135
Debug Data Break on Load/Store Exception
136
Debug Mode Exceptions
136
Exceptions Taken in Debug Mode
136
Debug Mode Exception Processing
137
MIPS EJTAG Compliant Mode
138
Accelerated EJTAG Mode
138
ACC Mode Flag
138
EJTAG Control Register in ACC Mode (ECR_A)
138
Processor Access Address Register in ACC Mode (ADDRESS_A)
140
Processor Access Data Register in ACC Mode (DATA_A)
140
Debug Mode Address Space in Compliant Mode (am = 0)
141
Debug Mode Address Space in ACC Mode (am = 1)
141
Supported JTAG Instructions in ACC Mode
142
Revision History
143

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User Manuals: Ingenic XBurst 2 CPU Core Low Power

Ingenic XBurst 2 CPU Core Programming Manual (143 pages)

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