Sony WX-850BT Service Manual page 48

WX-850BT/900BT/900BTM
Pin No. Pin Name
61 DAO5
62 DVSS5
63 VDD1_3
64 VSS_2
65 XVSS3
66 XI
67 XO
68 XVDD3
69 ADVDD3
70 ADIN1
71 ADVREFL
72 ADVCM
73 ADVREFH
74 ADIN2
75 ADVSS3
76 MS
77, 78 BUS0, BUS1
79 BUS2
80 BUS3
81 BUCK
82 CCE
83 VDD3_2
84 VSS_3
85 RST
86 VDD1_4
87 PIO0
88 PIO1
89 PIO2
90 PIO3
91 PIO4
92 PIO5
93 PIO6
94 PIO7
95 PIO8/CDMON0
96 PIO9/CDMON1
97 TEST
98 PDO
99 TMAX
100 LPFN
48
I/O
O Audio signal (sub-ch) output to the electrical volume
- Ground terminal
- Power supply terminal (+1.5V)
- Ground terminal
- Ground terminal
I System clock input terminal (16.9344 MHz)
O System clock output terminal (16.9344 MHz)
- Power supply terminal (+3.3V)
- Power supply terminal (+3.3V)
I Audio signal (L-ch) input from the electrical volume
O Reference voltage output terminal
O Reference voltage output terminal
O Reference voltage output terminal
I Audio signal (R-ch) input from the electrical volume
- Ground terminal
Microprocessor interface mode selection signal input terminal
I
"L": serial interface, "H": parallel interface
I/O Serial data input/output terminal
O Serial data output to the system controller
I Serial data input from the system controller
I Serial data transfer clock signal input from the system controller
I Chip enable signal input from the system controller
- Power supply terminal (+3.3V)
- Ground terminal
I Reset signal input from the system controller
- Power supply terminal (+1.5V)
O Interrupt signal output to the system controller
O Request signal output to the system controller
I Gate signal input from the system controller
I Audio data input from the system controller
I Bit clock signal input from the system controller
I L/R sampling clock signal input from the system controller
I Muting on/off control signal input from the system controller
O Zero data detection signal output to the system controller
O Serial data output to the system controller
I Serial data transfer clock signal input from the system controller
I Test mode setting terminal
O EFM and PLCK phase difference signal output terminal
O TMAX detection result output terminal
I PLL circuit low-pass fi lter amplifi er inversion input terminal
Description
Fixed at "L" in this unit
Not used
"L": reset
Normally fi xed at "L"
"L": muting on