NEC 78GK0S/K 1+ Series Application Note page 17

• Assembly language program example (same content as in
program)
XMAIN CSEG UNIT
RESET_START:
MOVW AX,
MOVW SP,
MOV WDTM, #01101111B
MOV A,
BF A.4,
MOV P2,
CHECK_LVI:
BT A.0,
during LVI reset
MOV LVIS, #00000111B
SET1 LVION
MOV A,
WAIT_200US:
DEC A
BNZ $WAIT_200US
WAIT_LVI:
MOV WDTE, #0ACH
BT LVIF, $WAIT_LVI
SET1 LVIMD
MAIN_LOOP:
XOR P2,
MOV CNT120,
WAIT_120MS:
CALL !WAIT_1MS
DBNZ CNT120, $WAIT_120MS ;
MOV WDTE, #0ACH
BR $MAIN_LOOP
Remark The above-mentioned wait time (200
done in the sample program.
CHAPTER 4 SETTING METHODS
#STACKTOP
AX ;
Set the stack pointer
;
WDT overflow time = 2^20/fx = 131.07 ms
•
•
•
RESF ;
Read the reset source
$CHECK_LVI ;
Go to CHECK_LVI if not a reset by WDT
#00000001B ;
Light LED2
$SET_CLOCK ;
Omit subsequent LVI-related processing and go to SET_CLOCK
;
Set the low-voltage detection level (VLVI) to 2.85 V +-0.15 V
;
Enable the low-voltage detector operation
#40 ;
Assign the 200 us wait count value
0.5[us/clk] × 10[clk] × 40[count] = 200[us]
;
;
Clear the watchdog timer
Branch if VDD < VLVI
;
Set so that an internal reset signal is generated when VDD < VLVI
;
•
•
Clearing WDT before overflow
•
occurrence and restarting
counting
#00000001B ;
Reverse output of LED1
#120 ;
Assign the 120 ms wait count value
;
Subroutine call for a 1 ms wait
1[ms] × 120[count] = 120[ms]
;
Clear the watchdog timer
;
Go to the MAIN_LOOP
•
• Clearing WDT before
overflow occurrence and
•
restarting counting
μ
s) is calculated with f
Application Note U18847EJ1V0AN
[Example 1] described above and the sample
Setting the WDT overflow time
and operation clock
(CPU clock frequency) being 2 MHz, as
CPU
17