Asus AAEON COM-BYTC2 User Manual
Asus AAEON COM-BYTC2 User Manual

Asus AAEON COM-BYTC2 User Manual

Com express module

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COM-BYTC2
COM Express Module
r d
User 's Manual 3
Ed
Last Updated: October 12, 2021

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Summary of Contents for Asus AAEON COM-BYTC2

  • Page 1 COM-BYTC2 COM Express Module User ’s Manual 3 Last Updated: October 12, 2021...
  • Page 2 Copyright Notice This document is copyrighted, 2021. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means witho ut the prior written permission of the original manufacturer.
  • Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel®, Pentium®, Celeron®, and Xeon® are registered trademarks of Intel ⚫ Corporation Intel Core™ and Intel Atom™ are trademarks of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: I t em Quantity COM-BYTC2 ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Saf e ty Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 Chi na RoHS Requirements ( CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (C d) (C r(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○...
  • Page 10 Chi na RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements He xavalent Polybrominated Polybrominated C omponent Le ad Me rcury C admium C hromium Biphenyls Diphenyl Ethers (Pb) (Hg)
  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..............1 Specifications ....................
  • Page 12 3.4.6 Advanced: CSM Configuration............33 3.4.7 Advanced: SIO Configuration ............34 3.4.8 Advanced: Serial Port Configuration ..........35 Setup submenu: Chipset ................36 3.5.1 Chipset: North Bridge Configuration..........37 3.5.1.1 North Bridge Configuration: Display Control Config uration ..................38 3.5.2 Chipset: South Bridge Configuration ..........41 Setup submenu: Security ................
  • Page 13: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...
  • Page 14: Specifications

    1 .1 Spe cifications System F o rm Factor COM Express Compact Size, Type 2 CP U Intel® Atom™/ Celeron® Processor CP U Frequency Up to 1.91 GHz, J1900 Chip set Intel® Atom™/ Celeron® SoC Memory Type DDR3L 1333, SODIMM x 1 Max.
  • Page 15 Et hernet Intel® i210IT Gigabit Ethernet x 1 A ud io High Definition Audio Interface U SB Port USB2.0 x 7 Serial Port — HDD Interface SATA II x 1 PATA x 1 Exp ansion PCIe [x1] x 2 (up to 2 devices) PCI x 4 SMBus GP IO...
  • Page 16: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...
  • Page 17: Dimensions, Jumpers And Connectors

    Di mensions, Jumpers and Connectors Chapter 2 – Hardware Information...
  • Page 18 Chapter 2 – Hardware Information...
  • Page 19: List Of Jumpers

    2.2 Li st of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Lab el F unction SW 1 Auto Power Button Selection and clear CMOS 2.2 .1 Auto Power Button Switch (SW1) Auto Power Button Disable (Default) Auto Power Button E nable Cl e ar CMOS...
  • Page 20: List Of Connectors

    2.3 Li st of Connectors Please refer to the table below for all of the board’s jumpers that you can configure for your application Lab el F unction CN 1 TYPE2 ROW A/B Connector CN 2 TYPE2 ROW C/D Connector CN 3 eDP Connector CN 4...
  • Page 21: Type2 Row A/B Connector (Cn1)

    2.3.1 T YPE2 Row A/B Connector ( CN1) R o w A R o w B P in Sig nal P in Sig nal AN1_MDI3N LAN1_LED_LINK# LAN1_MDI3P LPC_FRAME# LAN1_LED_100# LPC_AD0 LAN1_LED_1000# LPC_AD1 LAN1_MDI2N LPC_AD2 LAN1_MDI2P LPC_AD3 LAN1_LED_LINK# None LAN1_MDI1N None A 10 LAN1_MDI1P B 10...
  • Page 22 R o w A R o w B P in Sig nal P in Sig nal A 24 CB_SLP_S4# B 24 PWRGD_CB A 25 None B 25 None A 26 None B 26 None A 27 PM_BATLOW# B 27 CB_WDT A 28 CB_SATA_LED# B 28...
  • Page 23 R o w A R o w B P in Sig nal P in Sig nal A 49 PCIE_CPPE0# B 49 CARRY_SYSRST# A 50 INT_SERIRQ B 50 CB_RESET# A 51 B 51 A 52 None B 52 None A 53 None B 53 None...
  • Page 24 R o w A R o w B P in Sig nal P in Sig nal A 74 LVDSA_DATA1# B 74 LVDSB_DATA1# A 75 LVDSA_DATA2 B 75 LVDSB_DATA2 A 76 LVDSA_DATA2# B 76 LVDSB_DATA2# A 77 LVDS_VDD_EN B 77 LVDSB_DATA3 A 78 LVDSA_DATA3 B 78...
  • Page 25: Type2 Row C/D Co Nnector (Cn2)

    R o w A R o w B P in Sig nal P in Sig nal A 99 CB_SRXD1X B 99 SCI# A 100 B 100 A 101 CB_STXD2X B 101 CB_FAN_PWM (Option) A 102 CB_SRXD2X B 102 CB_FAN_TACH (Option) A 103 PCH_LID# B 103...
  • Page 26 R o w C R o w D P in Sig nal P in Sig nal IDE_D13_R IDE_IOW#_R IDE_D1_R IDE_ACK#_R IDE_D14_R IDE_INTRQ_R IDE_RDY_R IDE_A0_R IDE_IOR#_R IDE_A1_R LPC_PME# IDE_A2_R PCI_GNT2# IDE_CS1#_R PCI_REQ2# IDE_CS3#_R PCI_GNT1# IDE_RST#_R PCI_REQ1# PCI_GNT3# PCI_GNT0# PCI_REQ3# PCI_REQ0# PCI_AD1 PCI_RESET# PCI_AD3 PCI_AD0...
  • Page 27 R o w C R o w D P in Sig nal P in Sig nal PCI_PERR# PCI_STOP# PCI_LOCK# PCI_TRDY# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_AD16 PCI_C_BE2# PCI_AD18 PCI_AD17 PCI_AD20 PCI_AD19 PCI_AD22 PCI_AD21 PCI_AD24 PCI_AD23 PCI_AD26 PCI_C_BE3# PCI_AD28 PCI_AD25 PCI_AD30 PCI_AD27 PCI_IRQC# PCI_AD29 PCI_IRQD# PCI_AD31...
  • Page 28 R o w C R o w D P in Sig nal P in Sig nal None None None None None None None None None None None None None None None None None None None None None None None None None None None...
  • Page 29 R o w C R o w D P in Sig nal P in Sig nal None None None None None None None None None None None None None None None None None None None None None None C100 D100 C101 None D101...
  • Page 30: Edp Function From Ddi To Edp (Cn3)

    R o w C R o w D P in Sig nal P in Sig nal C109 D109 C110 D110 2.3.3 E DP Function f rom DDI to EDP (CN3) P in P in Name Sig nal Type +VLCD +VLCD TX0- DIFF TX0+...
  • Page 31: Backlight (Cn4)

    P in P in Name Sig nal Type BKLT_EN_3.3S EPC_HPD +VLED +VLED +VLED +VLED 2.3.4 Backlight (CN4) P in P in Name Sig nal Type +VLED BKL_CTRL_3.3S BKL_EN_3.3S Chapter 2 – Hardware Information...
  • Page 32: Spi Flash Tool (Cn5)

    2.3.5 SPI FL ASH tool (CN5) P in P in Name Sig nal Type SPI_SO_F SPI_CLK_F +V3.3A_SPI SPI_SI_F SPI_CE0#_F 2.3.6 LPC ( CN6) P in P in Name Sig nal Type LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 +V3.3S LPC_FRAME# BUF_PLT_RST# PCI_CLK_SIO INT_SERIRQ_3P3 Chapter 2 –...
  • Page 33: Rtc Battery (Bat1)

    2.3.7 RTC Battery ( BAT1) P in P in Name Sig nal Type +V3.3A_RTC Chapter 2 – Hardware Information...
  • Page 34: List Of Leds

    2.4 Li st of LEDs Please refer to the table below for all of the board’s LEDs that you can find the status Lab el F unction LED1 SATA Detect LED2 (Blue) S0 Voltage LED3 (Red) S5 Voltage 2.5 Function Block Diagram Chapter 2 –...
  • Page 35: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...
  • Page 36: System Test And Initialization

    System Test and Initialization The board uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.
  • Page 37: Ami Bios Setup

    3.2 AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...
  • Page 38: Setup Submenu: Main

    3.3 Se tup submenu: Main Press Delete to enter Setup Chapter 3 – AMI BIOS Setup...
  • Page 39: Setup Submenu: Advanced

    3.4 Se tup submenu: Advanced Chapter 3 – AMI BIOS Setup...
  • Page 40: Advanced: Cpu Configuration

    3.4.1 Advanced: CPU Configuration Options summary: Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default EIST Disabled Optimal Default, Failsafe Default Enabled Chapter 3 – AMI BIOS Setup...
  • Page 41: Advanced: Ide Configuration (Ide)

    3.4.2 Advanced: IDE Configuration ( IDE) Options summary: SATA Mode IDE Mode AHCI Mode Optimal Default, Failsafe Default Chapter 3 – AMI BIOS Setup...
  • Page 42: Advanced: Usb Configuration

    3.4.3 Advanced: USB Configuration Options summary: Legacy USB Support Enabled Optimal Default, Failsafe Default Disabled Auto Enables BIOS Support for Legacy USB Support. When enabled, USB can be functional in legacy environment like DOS. AUTO option disables legacy support if no USB devices are connected Device Name (Emulation Auto Optimal Default, Failsafe Default...
  • Page 43: Advanced: On-Module H/W Monitor

    3.4.4 Advanced: On-Module H/W Monitor Chapter 3 – AMI BIOS Setup...
  • Page 44: Advanced: Power Management

    3.4.5 Advanced: Power Management Options summary: Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. Restore on Power Last State Loss Power On Power Off Optimal Default, Failsafe Default Select power state when power is re-applied after a power failure. RTC wake system Disabled Optimal Default, Failsafe Default...
  • Page 45: Advanced: Csm Configuration

    3.4.6 Advanced: CSM Configuration Options summary: CSM Support Disabled Enabled Optimal Default, Failsafe Default Enable/Disable CSM Support Storage Do not launch UEFI Legacy Optimal Default, Failsafe Default Controls the execution of UEFI and Legacy storage OpROM Video Do not launch UEFI Legacy Optimal Default, Failsafe Default...
  • Page 46: Advanced: Sio Configuration

    3.4.7 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...
  • Page 47: Advanced: Serial Port Configuration

    3.4.8 Advanced: Serial Port Configuration Options summary: Use This Device Disabled Enabled Optimal Default, Failsafe Default En/Disable Serial Port (COM) Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2D8; IRQ=11; IO=2C8; IRQ=11; Select an optimal setting for IO device Chapter 3 – AMI BIOS Setup...
  • Page 48: Setup Submenu: Chipset

    3.5 Se tup submenu: Chipset Chapter 3 – AMI BIOS Setup...
  • Page 49: Chipset: North Bridge Configuration

    3.5.1 Chi pset: North Bridge Configuration Chapter 3 – AMI BIOS Setup...
  • Page 50 3.5.1.1 Nor th Bridge Configuration: Display Control Configuration Options summary: DVMT Pre-Allocated Optimal Default, Failsafe Default 128M 160M … 512M DVMT Total Gfx Mem 128MB 256MB Optimal Default, Failsafe Default Primary IGFX Boot VBIOS Default Optimal Default, Failsafe Default Display LVDS DP/HDMI Chapter 3 –...
  • Page 51 Select the Video Device which will be activated during POST. This has no effect if external graphics present. Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display Secondary IGFX Boot Disabled Optimal Default, Failsafe Default Display...
  • Page 52 Chapter 3 – AMI BIOS Setup...
  • Page 53: Chipset: South Bridge Configuration

    3.5.2 Chi pset: South Bridge Configuration Options summary: Audio Controller Enabled Optimal Default, Failsafe Default Disabled Chapter 3 – AMI BIOS Setup...
  • Page 54: Setup Submenu: Security

    3.6 Se tup submenu: Security Change User/Administrator Password Y ou can set a User Password once an Administrator Password is set. The password will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility.
  • Page 55: Setup Submenu: Boot

    Highlight this item and type in the current password. At the next dialog box press Enter to disable password protection. 3.7 Se tup submenu: Boot Options summary: Quiet Boot Disabled Enabled Default En/Disable showing boot logo. Option ROM Messages Force BIOS Default Keep Current Set display mode for Option ROM...
  • Page 56 This option controls Legacy/UEFI ROMs priority Chapter 3 – AMI BIOS Setup...
  • Page 57: Boot: Hard Drive Bbs Priorities

    3.7.1 Boot: Hard Drive BBS Priorities Chapter 3 – AMI BIOS Setup...
  • Page 58: Setup Submenu: Save & Exit

    3.8 Se tup submenu: Save & Exit Chapter 3 – AMI BIOS Setup...
  • Page 59: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...
  • Page 60: Driver Download/Installation

    Dri ver Download/Installation Drivers for the COM-BYTC2 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/modulescom-express-modules-com-bytc2 Download the driver(s) you need and follow the steps below to install them . St ep 1 – Install Chipset Driver Open the St ep1 - Chipset folder followed by SetupChipset.exe Follow the instructions Drivers will be installed automatically...
  • Page 61 St ep 4 – Install xHCI Driver Open the STEP4 - xHCI folder followed by Set up.exe Follow the instructions Drivers will be installed automatically St ep 5 – Install Intel Sideband Fabric Device Driver Open the STEP5 –Intel Sideband Fabric Device folder followed by Setup.exe Follow the instructions Drivers will be installed automatically St ep 6 –...
  • Page 62: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...
  • Page 63: Watchdog Timer Initial Program

    Watchdog T imer Initial Program Tab le 1 : Embedded BRAM relative register table Default Value N o te I nd ex 0x284(Note1) BRAM Index Register Dat a 0x285(Note2) BRAM Data Register Lo g ical Device Number 0xA 8(Note3) Watch dog Logical Device Number F unction and Device Number 0x00(Note4) Watch dog Function/Device Number...
  • Page 64 ************************************************************************************ // Embedded BRAM relative definition (Please reference to Table 1) #d efine byte EcBRAMIndex //This parameter is represented from N o te1 #d efine byte EcBRAMData //This parameter is represented from N ote2 #d efine byte BRAMLDNReg //This parameter is represented from N o te3 #d efine byte BRAMFnDataReg //This parameter is represented from N o te4 #d efine vo id EcBRAMWriteByte(byte Offset, b yte Value);...
  • Page 65 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 66 ************************************************************************************ // Procedure : AaeonWDTEnable VOID A aeonWDTEnable (){ WDTEnableDisable(1); // Procedure : AaeonWDTConfig VOID A aeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(0); // WDT relative parameter setting WDTParameterSetting(); VOID W DTEnableDisable(byte Value){ ECBRAMWriteByte(TimerReg , Value); VOID W DTParameterSetting(){ Byte TempByte; // Watchdog Timer counter setting ECBRAMWriteByte(TimerReg , TimerVal);...
  • Page 67 ************************************************************************************ VOID ECB RAMWriteByte(byte OPReg, byte OPBit, byte Value){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x13 + OPReg); IOWriteByte(EcBRAMData, Value); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x30); //Write start Byte ECBRAMReadByte(byte OPReg){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x12);...
  • Page 68: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...
  • Page 69: I/O Address Map

    I/O Address Map Appendix B – I/O Informati o n...
  • Page 70 Appendix B – I/O Informati o n...
  • Page 71: Memory Address Map

    B.2 Me m or y Address Map Appendix B – I/O Informati o n...
  • Page 72: Irq Mapping Chart

    B.3 IRQ Mapping Chart Appendix B – I/O Informati o n...
  • Page 73 Appendix B – I/O Informati o n...
  • Page 74 Appendix B – I/O Informati o n...
  • Page 75 Appendix B – I/O Informati o n...
  • Page 76 Appendix B – I/O Informati o n...
  • Page 77 Appendix B – I/O Informati o n...
  • Page 78 Appendix B – I/O Informati o n...
  • Page 79 Appendix B – I/O Informati o n...
  • Page 80 Appendix B – I/O Informati o n...
  • Page 81 Appendix B – I/O Informati o n...
  • Page 82 Appendix B – I/O Informati o n...
  • Page 83 Appendix B – I/O Informati o n...
  • Page 84: Appendix C - Programming Digital I/O

    Appendix C Appendix C – Programming Digital I/O...
  • Page 85: Digital I/O Register

    Di gital I/O Register Tab le 1 : Embedded BRAM relative register table Default Value N o te I nd ex 0x284(Note1) BRAM Index Register Dat a 0x285(Note2) BRAM Data Register Lo g ical Device Number 0xA 2(Note3) Watch dog Logical Device Number I np ut/Output DIO Input/Output Function/Device 0x00(Note4)
  • Page 86: Digital I/O Sample Program

    C.2 Di gital I/O Sample Program ************************************************************************************ // Embedded BRAM relative definition (Please reference to Table 1) #d efine byte EcBRAMIndex //This parameter is represented from N o te1 #d efine byte EcBRAMData //This parameter is represented from N ote2 #d efine byte BRAMLDNReg //This parameter is represented from N o te3 #d efine byte BRAMFnData0Reg //This parameter is represented from N o te4 #d efine byte BRAMFnData1Reg //This parameter is represented from N o te5...
  • Page 87 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DI O0ToDIO7Reg, DIO3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 88 ************************************************************************************ Boolean A aeonReadPinStatus(byte OptionReg, byte BitNum) { Byte TempByte; TempByte = ECBRAMReadByte(BRAMFnData1Reg, OptionReg); If (TempByte & BitNum == 0) Return 0; Return 1; VOID A aeonSetOutputLevel(byte OptionReg, byte BitNum, byte Value){ Byte TempByte; TempByte = ECBRAMReadByte(BRAMFnData1Reg, OptionReg); TempByte |= (Value << BitNum); ECBRAMWriteByte(OptionReg, BitNum, Value);...
  • Page 89 ************************************************************************************ VOID ECB RAMWriteByte(byte OPReg, byte OPBit, byte Value){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x13 + OPReg); IOWriteByte(EcBRAMData, Value); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x30); //Write start Byte ECBRAMReadByte(byte FnDataReg, byte OPReg){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, FnDataReg);...
  • Page 90: Appendix D -Notes For Users

    Appendix D Appendix D –Notes for Users...
  • Page 91: Notes For Users

    Note s for Users Please observe the following items to ensure optimal performance: eDP limitation Display Default: CRT + LVDS If you want to use the onboard eDP, please contact AAEON tech support for the BIOS that support onboard eDP. Due to the limitation, eDP works only on major OS and no display in DOS environment.

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