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Asus Aaeon COM-ICDB7 User Manual

Asus Aaeon COM-ICDB7 User Manual

Com express cpu module
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COM-ICDB7
COM Express CPU Module
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User's Manual 4
Ed
Last Updated: February 10, 2025

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Summary of Contents for Asus Aaeon COM-ICDB7

  • Page 1 COM-ICDB7 COM Express CPU Module User’s Manual 4 Last Updated: February 10, 2025...

  • Page 2: Copyright Notice

    Copyright Notice This document is copyrighted, 2025. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft® Windows® is a registered trademark of Microsoft Corp. ⚫ Intel® and Xeon® are registered trademarks of Intel Corporation ⚫ ITE is a trademark of Integrated Technology Express, Inc. ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity COM-ICDB7 ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON 主板/子板/背板 QO4-381 Rev.A2 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 本表格依据 SJ/T 11364 的规定编制。 ○：表示该有毒有害物质在该部件所有均质材料中的含量均在GB/T 26572标准规定...
  • Page 10 China RoHS Requirement (EN) Name and content of hazardous substances in product AAEON Main Board/Daughter Board/Backplane QO4-381 Rev.A2 Hazardous Substances 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 Part Name (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB Assemblies × ○ ○ ○ ○...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Function Block Diagram ..................4 Chapter 2 – Hardware Information ..................5 Dimensions ....................... 6 Switches and Connectors ..................8 List of Connectors ....................10 2.3.1 AT/ATX Switch (SW1) .................. 11 2.3.2 Battery (CN3) ....................
  • Page 12 3.4.3 Hardware Monitor ..................33 3.4.4 SIO Configuration ..................34 3.4.5 Serial Port Configuration ................35 3.4.6 Serial Port Console Redirection .............. 36 3.4.7 AAEON BIOS Robot .................. 37 3.4.8 Power Management .................. 39 3.4.9 Digital IO Port Configuration ..............40 Setup Submenu: Platform Configuration ............41 3.5.1 PCH-IO Configuration ................
  • Page 13 I/O Address Map ....................62 Memory Address Map ..................64 IRQ Mapping Chart ....................65 Preface XIII...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor PICMG COM Express R3.0, Type 7 Intel® Xeon® D-1848TER (10C/20T, 2.00 GHz, 57W) Intel® Xeon® D-1746TER (10C/20T, 2.00 GHz, 67W) Intel® Xeon® D-1735TR (8C/16T, 2.20 GHz, 59W) Intel® Xeon® D-1712TR (4C/4T, 2.00 GHz, 40W) Chipset Memory Type DDR4 SODIMM Socket x 4 Max.
  • Page 16 Ethernet 1GbE: Intel® Ethernet Controller I210-IT 10GbE: 10G Base-T to Carrier x 4 Audio — USB Port USB 2.0 x 4 USB 3.2 Gen 1 x 4 Serial Port 2-Wire UART (Tx/Rx) x 2 HDD Interface SATA 6Gb/s x 2 Expansion Slot PCIe [x16] x 1 PCIe [x4] X 4...

  • Page 17: Function Block Diagram

    Function Block Diagram Chapter 1 – Product Specifications...

  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 19: Dimensions

    Dimensions Chapter 2 – Hardware Information...
  • Page 20 With Heat Spreader: With Active Cooler: Chapter 2 – Hardware Information...

  • Page 21: Switches And Connectors

    Switches and Connectors Top Side Chapter 2 – Hardware Information...
  • Page 22 Bottom Side Chapter 2 – Hardware Information...

  • Page 23: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s switches and connectors that you can configure for your application Label Function AT/ATX Switch DDR4 SODIMM Socket DDR4 SODIMM Socket Battery SPI Debug Port (EC) SPI Debug Port (BIOS) DDR4 SODIMM Socket DDR4 SODIMM Socket Row A/B...

  • Page 24: At/Atx Switch (Sw1)

    2.3.1 AT/ATX Switch (SW1) AT Mode ATX Mode RTC Reset RTC Normal 2.3.2 Battery (CN3) Signal +3.3V 2.3.3 SPI Debug Port (EC) (CN4) Signal SPI_MISO SPI_CLK +3.3VSB SPI_MOSI SPI_CS 2.3.4 SPI Debug Port (BIOS) (CN5) Signal SPI_MISO SPI_CLK +3.3VSB SPI_MOSI Chapter 2 –...

  • Page 25: Row A/B Connector (Cn8)

    Signal SPI_CS 2.3.5 Row A/B Connector (CN8) Row A Row B Signal Signal GND(FIXED) GND(FIXED) GBE0_MDI3- GBE0_ACT# GBE0_MDI3+ LPC_FRAME# GBE0_LINK100# LPC_AD0 GBE0_LINK1000# LPC_AD1 GBE0_MDI2- LPC_AD2 GBE0_MDI2+ LPC_AD3 GBE0_LINK# LPC_DRQ0# GBE0_MDI1- LPC_DRQ1# GBE0_MDI1+ LPC_CLK GND(FIXED) GND(FIXED) GBE0_MDI0- PWRBTN# GBE0_MDI0+ SMB_CK GBE0_CTREF SMB_DAT SUS_S3# SMB_ALERT#...
  • Page 26 Row A Row B Signal Signal PCIE_TX14- PCIE_RX14- BATLOW# (S)ATA_ACT# RSVD RSVD RSVD RSVD RSVD GND(FIXED) GND(FIXED) RSVD SPKR RSVD I2C_CK BIOS_DIS0# I2C_DAT THRMTRIP# THRM# PCIE_TX13+ PCIE_RX13+ PCIE_TX13- PCIE_RX13- PCIE_TX12+ PCIE_RX12+ PCIE_TX12- PCIE_RX12- GND(FIXED) GND(FIXED) USB2- USB3- USB2+ USB3+ USB_2_3_OC# USB_0_1_OC# USB0- USB1-...
  • Page 27 Row A Row B Signal Signal PCIE_TX3+ PCIE_RX3+ PCIE_TX3- PCIE_RX3- GND(FIXED) GND(FIXED) PCIE_TX2+ PCIE_RX2+ PCIE_TX2- PCIE_RX2- GPI1 GPO3 PCIE_TX1+ PCIE_RX1+ PCIE_TX1- PCIE_RX1- WAKE0# GPI2 WAKE1# PCIE_TX0+ PCIE_RX0+ PCIE_TX0- PCIE_RX0- GND(FIXED) GND(FIXED) PCIE_TX8+ PCIE_RX8+ PCIE_TX8- PCIE_RX8- PCIE_TX9+ PCIE_RX9+ PCIE_TX9- PCIE_RX9- PCIE_TX10+ PCIE_RX10+ PCIE_TX10- PCIE_RX10-...

  • Page 28: Row C/D Connector (Cn9)

    Row A Row B Signal Signal GND(FIXED) GND(FIXED) SPI_POWER NCSI_CLK_IN SPI_MISO NCSI_RXD1 GPO0 NCSI_RXD0 SPI_CLK NCSI_CRS_DV SPI_MOSI NCSI_TXD1 TPM_PP NCSI_TXD0 TYPE10# SPI_CS# SER0_TX NCSI_ARB_IN SER0_RX NCSI_ARB_OUT A100 GND(FIXED) B100 GND(FIXED) A101 SER1_TX B101 FAN_PWMOUT A102 SER1_RX B102 FAN_TACHIN A103 LID# B103 SLEEP# A104...
  • Page 29 Row C Row D Signal Signal USB_SSRX1- USB_SSTX1- USB_SSRX1+ USB_SSTX1+ USB_SSRX2- USB_SSTX2- USB_SSRX2+ USB_SSTX2+ GND(FIXED) GND(FIXED) USB_SSRX3- USB_SSTX3- USB_SSRX3+ USB_SSTX3+ 10G_PHY_MDC_SCL3 10G_PHY_MDIO_SDA3 10G_PHY_MDC_SCL2 10G_PHY_MDIO_SDA2 10G_SDP2 10G_SDP3 PCIE_RX6+ PCIE_TX6+ PCIE_RX6- PCIE_TX6- GND(FIXED) GND(FIXED) PCIE_RX7+ PCIE_TX7+ PCIE_RX7- PCIE_TX7- 10G_INT2 10G_INT3 10G_KR_RX3+ 10G_KR_TX3+ 10G_KR_RX3- 10G_KR_TX3- 10G_KR_RX2+...
  • Page 30 Row C Row D Signal Signal 10G_SFP_SDA1 10G_SFP_SCL1 10G_SFP_SDA0 10G_SFP_SCL0 10G_SDP0 10G_SDP1 GND(FIXED) GND(FIXED) 10G_KR_RX1+ 10G_KR_TX1+ 10G_KR_RX1- 10G_KR_TX1- 10G_PHY_MDC_SCL1 10G_PHY_MDIO_SDA1 10G_PHY_MDC_SCL0 10G_PHY_MDIO_SDA0 10G_INT0 10G_INT1 10G_KR_RX0+ 10G_KR_TX0+ 10G_KR_RX0- 10G_KR_TX0- GND(FIXED) GND(FIXED) PCIE_RX16+ PCIE_TX16+ PCIE_RX16- PCIE_TX16- TYPE0# RSVD PCIE_RX17+ PCIE_TX17+ PCIE_RX17- PCIE_TX17- TYPE1# TYPE2# PCIE_RX18+...
  • Page 31 Row C Row D Signal Signal GND(FIXED) GND(FIXED) PCIE_RX22+ PCIE_TX22+ PCIE_RX22- PCIE_TX22- PCIE_RX23+ PCIE_TX23+ PCIE_RX23- PCIE_TX23- RSVD RSVD PCIE_RX24+ PCIE_TX24+ PCIE_RX24- PCIE_TX24- GND(FIXED) GND(FIXED) PCIE_RX25+ PCIE_TX25+ PCIE_RX25- PCIE_TX25- RSVD RSVD PCIE_RX26+ PCIE_TX26+ PCIE_RX26- PCIE_TX26- PCIE_RX27+ PCIE_TX27+ PCIE_RX27- PCIE_TX27- GND(FIXED) GND(FIXED) PCIE_RX28+ PCIE_TX28+ PCIE_RX28-...

  • Page 32: Lpc (Cn10)

    Row C Row D Signal Signal C102 PCIE_RX31- D102 PCIE_TX31- C103 D103 C104 VCC_12V D104 VCC_12V C105 VCC_12V D105 VCC_12V C106 VCC_12V D106 VCC_12V C107 VCC_12V D107 VCC_12V C108 VCC_12V D108 VCC_12V C109 VCC_12V D109 VCC_12V C110 GND(FIXED) D110 GND(FIXED) 2.3.7 LPC (CN10) Signal...
  • Page 33 Signal SDP3 SDP4 Chapter 2 – Hardware Information...

  • Page 34: Hardware Assembly

    Hardware Assembly 2.4.1 CPU Cooler Assembly Step 1: Note: Slightly tighten all four screws in diagonal order. Then, repeat with torque 3-5 kgf-cm with proper tools. Note: According to the CPU spec, the CPU case should be kept at or below 85°C for your thermal design consideration.
  • Page 35 Step 2: Chapter 2 – Hardware Information...

  • Page 36: Heat Spreader Assembly

    2.4.2 Heat Spreader Assembly Step 1: Note: Slightly tighten all four screws in diagonal order. Then, repeat with torque 3-5 kgf-cm with proper tools Note: According to the CPU spec, the CPU Tcase should be kept at or below 85°C for your thermal design consideration.
  • Page 37 Step 2: Chapter 2 – Hardware Information...

  • Page 38: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 39: System Test And Initialization

    System Test and Initialization These routines test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are two kinds of errors: fatal and non-fatal. The system can usually continue the boot up sequence with non-fatal errors.

  • Page 40: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 41: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 42: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 43: Trusted Computing

    3.4.1 Trusted Computing Options Summary Security Device Support Enable Optimal Default, Failsafe Default Disable Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Optimal Default, Failsafe Default Enabled...
  • Page 44 Options Summary Enable or Disable SM3_256 PCR Bank. Pending operation None Optimal Default, Failsafe Default TPM Clear Schedule an Operation for the Security Device. Note: Your Computer will reboot during restart in order to change State of Security Device. Platform Hierarchy Enabled Optimal Default, Failsafe Default Disabled...

  • Page 45: Nvme Configuration

    3.4.2 NVMe Configuration Chapter 3 – AMI BIOS Setup...

  • Page 46: Hardware Monitor

    3.4.3 Hardware Monitor Options Summary System Fan Full Mode Optimal Default, Failsafe Default Manual Mode by PWM Auto Mode by PWM PWM signal Non-inverting Optimal Default, Failsafe Default Inverting Select output PWM of inverting or non-uninverting signal. Chapter 3 – AMI BIOS Setup...

  • Page 47: Sio Configuration

    3.4.4 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 48: Serial Port Configuration

    3.4.5 Serial Port Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 49: Serial Port Console Redirection

    3.4.6 Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Console Redirection EMS Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup...

  • Page 50: Aaeon Bios Robot

    3.4.7 AAEON BIOS Robot Options Summary Sends watch dog before Disabled Optimal Default, Failsafe Default BIOS POST Enabled Enabled - Robot set Watch Dog Timer (WDT) right after power on, before BIOS start POST process. And then Robot will clear WDT on completion of POST. WDT will reset system automatically if it is not cleared before its timer counts down to zero.
  • Page 51 Options Summary Timer count set to Watch Dog Timer for OS loading. Delayed POST (PEI phase) Disabled Optimal Default, Failsafe Default Enabled Enabled - Robot holds BIOS from starting POST, right after power on. This allows BIOS POST to start with stable power or start after system is physically warmed-up. Note: Robot does this before 'Sends watch dog'.

  • Page 52: Power Management

    3.4.8 Power Management Options Summary Power Mode ATX Type AT Type Optimal Default, Failsafe Default Select power supply mode. Restore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off Select power state when power is re-applied after a power failure. RTC wake system from S5 Disable Optimal Default, Failsafe Default...

  • Page 53: Digital Io Port Configuration

    3.4.9 Digital IO Port Configuration Options Summary DIO Port* Output Input Set DIO as Input or Output. Output Level High Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...

  • Page 54: Setup Submenu: Platform Configuration

    Setup Submenu: Platform Configuration Chapter 3 – AMI BIOS Setup...

  • Page 55: Pch-Io Configuration

    3.5.1 PCH-IO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 56: Pci Express Configuration

    3.5.2 PCI Express Configuration Options Summary PCI Express Root Port* Disabled Enabled Optimal Default, Failsafe Default Control the PCI Express Root Port. ASPM Disabled Enabled Optimal Default, Failsafe Default Control the PCI Express Root Port. PCI Express Root Port* Disabled Optimal Default, Failsafe Default L0sL1 Auto...

  • Page 57: Sata Configuration

    Options Summary PCIe Speed Cont. Gen2 Gen3 Optimal Default, Failsafe Default Configure PCIe Speed Auto is equal to Gen2 or Gen3 depending on DTR soft strap. 3.5.3 SATA Configuration Options Summary SATA Configuration Enabled Optimal Default, Failsafe Default Disabled SATA test settings. Port* Enabled Optimal Default, Failsafe Default...

  • Page 58: Server Me Configuration

    3.5.4 Server ME Configuration Chapter 3 – AMI BIOS Setup...

  • Page 59: Setup Submenu: Socket Configuration

    Setup Submenu: Socket Configuration Chapter 3 – AMI BIOS Setup...

  • Page 60: Processor Configuration

    3.6.1 Processor Configuration Options Summary Hyper-Threading [ALL] Disable Enable Optimal Default, Failsafe Default Enable Hyper Threading (Software Method to Enable/Disable Logical Processor threads). Chapter 3 – AMI BIOS Setup...

  • Page 61: Memory Configuration

    3.6.2 Memory Configuration Options Summary Memory Frequency 2400 Optimal Default, Failsafe Default 2666 2933 Maximum Memory Frequency Selections in Mhz. If Enforce POR is disabled, user will be able to run at higher frequencies than the memory support (limited by processor support).

  • Page 62: Memory Topology

    3.6.3 Memory Topology Chapter 3 – AMI BIOS Setup...

  • Page 63: Iio Configuration

    3.6.4 IIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 64: Socket0 Configuration

    3.6.5 Socket0 Configuration Options Summary IOU0 (IIO PCIe Port 1) Auto Optimal Default, Failsafe Default X4X4X4X4 X4X4X8 X8X4X4 X8X8 Selects PCIe port Bifurcation for selected slot(s). Chapter 3 – AMI BIOS Setup...

  • Page 65: Setup Submenu: Security

    Setup Submenu: Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.

  • Page 66: Secure Boot

    3.7.1 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 67: Key Management

    3.7.2 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Restore Factory Keys Force System to User Mode.
  • Page 68 Options Summary Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db). Restore DB defaults Restore DB variable to factory defaults Platform Key (PK) Details Export Update Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures...

  • Page 69: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Quiet Boot option. UEFI PXE Support Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. FIXED BOOT ORDER Priorities Sets the system boot order Chapter 3 –...

  • Page 70: Bbs Priorities

    3.8.1 BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 71: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Options Summary Save Changes and Reset Reset the system after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Restore Defaults Restore/Load Default values for all the setup options. Chapter 3 – AMI BIOS Setup...

  • Page 72: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 73: Drivers Download And Installation

    Drivers Download and Installation Drivers for the COM-ICDB7 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/com-express-cpu-modules-com-icdb7 Download the driver(s) you need and follow the steps below to install them. Chipset Driver (Windows 10) Open the folder where you unzipped the Chipset Drivers Run the SetupChipset.exe file in the folder Follow the instructions...

  • Page 74: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...
  • Page 75 I/O Address Map Appendix A - I/O Information...
  • Page 76 Appendix A - I/O Information...

  • Page 77: Memory Address Map

    A.2 Memory Address Map Appendix A - I/O Information...

  • Page 78: Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A - I/O Information...
  • Page 79 Appendix A - I/O Information...
  • Page 80 Appendix A - I/O Information...