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Lauterbach C2000 Manual

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C2000 Debugger

Release 02.2023
MANUAL

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Summary of Contents for Lauterbach C2000

  • Page 1: C2000 Debugger

    C2000 Debugger Release 02.2023 MANUAL...

  • Page 2: Table Of Contents

     ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... TI DSPs ............................. C2000 Debugger ........................History ..........................Introduction ........................Brief Overview of Documents for New Users Demo and Start-up Scripts Converter from GEL to PRACTICE .................. Warning ..........................
  • Page 3 Turn ERAD features off ERAD.ON Turn ERAD features on JTAG Connection ......................Mechanical Description of the 20-pin Debug Cable Electrical Description of the 20-pin Debug Cable Mechanical Description of the TI Connector FAQ ............................. Operation Voltage ......................1989-2023 © Lauterbach C2000 Debugger...

  • Page 4: History

    C2000 Debugger Version 10-Feb-2023 History 23-Nov-22 New command SYStem.Option.ExecutionMode. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 5: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.

  • Page 6: Converter From Gel To Practice

    Code Composer Studio’s usefulness. The converter allows you to convert GEL language into PRACTICE scripts (*.cmm), which can be used directly in TRACE32. For more detailed information on that converter please refer to “Converter from GEL to PRACTICE” (converter_gel.pdf). 1989-2023 © Lauterbach C2000 Debugger...

  • Page 7: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 8: Dsp Specific Implementations

    On-chip Breakpoints for Data To stop the CPU after a read or write access to a memory location on-chip breakpoints are required. In the DSP notation these breakpoints are called watch points (WP). 1989-2023 © Lauterbach C2000 Debugger...

  • Page 9: Memory Classes

    To access a memory class, write the class in front of the address. Prepending an E as attribute to the memory class will make memory accesses possible, even when the target CPU is running. See SYStem.MemAccess SYStem.CpuAccess for more information. Examples: Data.dump D:0--0xff Data.Dump ED:0x8000 Data.List EP:main 1989-2023 © Lauterbach C2000 Debugger...

  • Page 10: Dsp Specific System Commands

    Level Test Access Port. The debugger might need to control it in order to reconfigure the JTAG chain or to control power, clock, reset, and security of different chip components. For descriptions of the commands on the MultiTap tab, see MultiTap. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 11: System.config

    SWDPTargetSel <value> TriState [ON | OFF] <parameter>: DAPDRPOST <bits> DAPDRPRE <bits> (JTAG cont.) DAPIRPOST <bits> DAPIRPRE <bits> DRPOST <bits> DRPRE <bits> ETBDRPOST <bits> (C5000 only) ETBDRPRE <bits> (C5000 only) ETBIRPOST<bits> (C5000 only) ETBIRPRE <bits> (C5000 only) 1989-2023 © Lauterbach C2000 Debugger...
  • Page 12 APBAPn.XtorName <name> AXIAPn.ACEEnable [ON | OFF] AXIAPn.Base <address> AXIAPn.CacheFlags <value> AXIAPn.HPROT [<value> | <name>] AXIAPn.Port <port> AXIAPn.RESet AXIAPn.view AXIAPn.XtorName <name> DEBUGAPn.Port <port> DEBUGAPn.RESet DEBUGAPn.view DEBUGAPn.XtorName <name> JTAGAPn.Base <address> JTAGAPn.Port <port> JTAGAPn.CorePort <port> JTAGAPn.RESet JTAGAPn.view JTAGAPn.XtorName <name> 1989-2023 © Lauterbach C2000 Debugger...
  • Page 13 DRM.Base <address> DRM.RESet DRM.view EPM.Base <address> EPM.RESet EPM.view ETB.ATBSource <source> ETB.Base <address> ETB.Name <string> ETB.NoFlush [ON | OFF] ETB.RESet ETB.Size <size> ETB.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL- STOP | FULLCTI] ETB.view 1989-2023 © Lauterbach C2000 Debugger...
  • Page 14 TBR.Base <address> TBR.Name <string> TBR.NoFlush [ON | OFF] TBR.RESet TBR.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL- STOP | FULLCTI] TBR.view TPIU.ATBSource <source> TPIU.Base <address> TPIU.Name <string> TPIU.RESet TPIU.Type [CoreSight | Generic] TPIU.view 1989-2023 © Lauterbach C2000 Debugger...
  • Page 15 TRACETPIUFUNNELPORT <port> view AHBACCESSPORT <port> APBACCESSPORT <port> AXIACCESSPORT <port> COREJTAGPORT <port> DEBUGACCESSPORT <port> JTAGACCESSPORT <port> MEMORYACCESSPORT <port> The SYStem.CONFIG commands inform the debugger about the available on-chip debug and trace components and how to access them. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 16 This is a common description of the SYStem.CONFIG command group for the TI C2000, C5000, C6000 and C7000 DSPs. Each debugger will provide only a subset of these commands. Some commands need a certain CPU type selection (SYStem.CPU <type>) to become active and it might additionally depend on further settings.

  • Page 17: Parameters> Describing The "Debugport

    But sometimes it is a must to tell the debugger that these cores share resources on the same <chip>. Whereby the “chip” does not need to be identical with the device on your target board: debugger#1: <core>=1 <chip>=1 debugger#2: <core>=2 <chip>=1 1989-2023 © Lauterbach C2000 Debugger...
  • Page 18 JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). The other debuggers need to have the setting Slave ON. Default: OFF. Default: ON if CORE=... >1 in the configuration file (e.g. config.t32). 1989-2023 © Lauterbach C2000 Debugger...
  • Page 19 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 20: Parameters> Describing The "Jtag" Scan Chain And Signal Behavior

    TDO signal. See possible TAP types and example below. Default: 0. NOTE: If you are not sure about your settings concerning IRPRE, IRPOST, DRPRE, and DRPOST, you can try to detect the settings automatically with the SYStem.DETECT.DaisyChain command. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 21 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 22 Example: ARM11 TAP ETB TAP OfNoInterest TAP DAP TAP IR: 5bit IR: 4bit IR: 7bit IR: 4bit SYStem.CONFIG IRPRE 15. SYStem.CONFIG DRPRE SYStem.CONFIG DAPIRPOST 16. SYStem.CONFIG DAPDRPOST SYStem.CONFIG ETBIRPOST SYStem.CONFIG ETBDRPOST SYStem.CONFIG ETBIRPRE SYStem.CONFIG ETBDRPRE 1989-2023 © Lauterbach C2000 Debugger...
  • Page 23 1989-2023 © Lauterbach C2000 Debugger...

  • Page 24: Parameters> Describing A System Level Tap "Multitap

    TAP in the JTAG chain. E.g. ARM11 TAP if you intend to debug an ARM11. Used if MULTITAP=Icepickx. ETBTAP <tap> Specifies the TAP number which needs to be activated to get the ETB TAP in the JTAG chain. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 25 Number of a Non-JTAG Control Register (NJCR) which shall be used by the debugger. Used if MULTITAP=Icepickx. SLAVETAP <tap> Specifies the TAP number to get the Icepick of the sub-system in the JTAG scan chain. Used if MULTITAP=IcepickXY (two Icepicks). 1989-2023 © Lauterbach C2000 Debugger...

  • Page 26: Parameters> Configuring A Coresight Debug Access Port "Ap

    “Port” or “Base” (with “DP:” access) in case XtorName remains empty. Example 1: SoC-400 SoC-400 ROM table Memory Access Port CoreSight (MEM-AP) Component Debug ROM table Memory Port Access Port (DP) (MEM-AP) CoreSight Component JTAG Access Port (JTAG-AP) 1989-2023 © Lauterbach C2000 Debugger...
  • Page 27 MEMORYAPn.HPROT Default: 0. [<value> | <name>] This option selects the value used for the HPROT bits in the Control Status Word (CSW) of a CoreSight Memory Access Port, when using the E: memory class. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 28 =0x06: Domain=0x0, Cache=0x6 ReadAllocateInnerShareable =0x16: Domain=0x1, Cache=0x6 ReadAllocateOuterShareable =0x26: Domain=0x2, Cache=0x6 WriteAllocateNonShareable =0x0A: Domain=0x0, Cache=0xA WriteAllocateInnerShareable =0x1A: Domain=0x1, Cache=0xA WriteAllocateOuterShareable =0x2A: Domain=0x2, Cache=0xA ReadWriteAllocateNonShareable =0x0E: Domain=0x0, Cache=0xE ReadWriteAllocateInnerShareable =0x1E: Domain=0x1, Cache=0xE ReadWriteAllocateOuterShareable =0x2E: Domain=0x2, Cache=0xE 1989-2023 © Lauterbach C2000 Debugger...
  • Page 29 ..RESet Undo the configuration for this access port. This does not cause a physical reset for the access port on the chip..view Opens a window showing the current configuration of the access port. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 30 AP access port number (0-255) of a SoC-400 system where MEMORYACCESSPORT system memory can be accessed even during runtime (typically <port> (deprecated) an AHB). Used for “E:” access class while running, assuming “SYStem.MemAccess DAP”. Default: <port>=0. SoC-600 Specific Commands 1989-2023 © Lauterbach C2000 Debugger...
  • Page 31 Example: SYStem.CONFIG.JTAGAP1.Base DP:0x80005000 Meaning: The control register block of the JTAG access ports starts at address 0x80005000. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 32: Parameters> Describing Debug And Trace "Components

    If you press the button with the three dots you get the corresponding command in the command line where you can view and maybe copy it into a script file. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 33 FUNNEL TPIU SYStem.CONFIG.COREDEBUG.Base 0x80010000 0x80012000 SYStem.CONFIG.BMC.Base 0x80011000 0x80013000 SYStem.CONFIG.ETM.Base 0x8001c000 0x8001d000 SYStem.CONFIG.STM1.Base EAHB:0x20008000 SYStem.CONFIG.STM1.Type ARM SYStem.CONFIG.STM1.Mode STPv2 SYStem.CONFIG.FUNNEL1.Base 0x80004000 SYStem.CONFIG.FUNNEL2.Base 0x80005000 SYStem.CONFIG.TPIU.Base 0x80003000 SYStem.CONFIG.FUNNEL1.ATBSource ETM.0 0 ETM.1 1 SYStem.CONFIG.FUNNEL2.ATBSource FUNNEL1 0 STM1 7 SYStem.CONFIG.TPIU.ATBSource FUNNEL2 1989-2023 © Lauterbach C2000 Debugger...
  • Page 34 HTM on port 1 and from STM on port 7. In an SMP (Symmetric MultiProcessing) debug session where you used a list of base addresses to specify one component per core you need to indicate which component in the list is meant: 1989-2023 © Lauterbach C2000 Debugger...
  • Page 35 ETM, ETR a list of base addresses to specify one component per core. Example assuming four cores: SYStem.CONFIG COREDEBUG.Base 0x80001000 0x80003000 0x80005000 0x80007000 For a list of possible components including a short description Components and Available Commands. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 36 ID (ETM.TraceID <id>). The default setting is typically fine because the debugger uses different default trace IDs for different components. For a list of possible components including a short description Components and Available Commands. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 37 It is possible that different funnels have the same address for their control register block. This assumes they are on different buses and for different cores. In this case it is needed to give the funnel different names to differentiate them. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 38 See the description of the commands above. Please note that there is a common description for ..ATBSource, ..Base, , ..RESet, ..TraceID. ADTF.Base <address> ADTF.RESet ADTF.Type [None | ADTF | ADTF2 | GEM] 1989-2023 © Lauterbach C2000 Debugger...
  • Page 39 REPlicatorB can be used from other ATB sinks to connect to output A or B to the Replicator. OCP.Base <address> OCP.RESet OCP.TraceID <id> OCP.Type <type> Open Core Protocol watchpoint unit (OCP) - Texas Instruments Trace source module delivering bus trace information to a system trace module. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 40 Trace source delivering system trace information e.g. sent by software in printf() style. TPIU.ATBSource <source> TPIU.Base <address> TPIU.RESet TPIU.Type [CoreSight | Generic] Trace Port Interface Unit (TPIU) - ARM CoreSight module Trace sink sending the trace off-chip on a parallel trace port (chip pins). 1989-2023 © Lauterbach C2000 Debugger...

  • Page 41: Parameters> Which Are "Deprecated

    RAM which accesses shall be traced. The trace packages include only relative addresses to PERBASE and RAMBASE. For a list of possible components including a short description Components and Available Commands. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 42 QV1: This mode is not yet used. TIOCPTYPE <type> Specifies the type of the OCP module from Texas Instruments (TI). view Opens a window showing most of the SYStem.CONFIG settings and allows to modify them. 1989-2023 © Lauterbach C2000 Debugger...
  • Page 43 ETMFUNNELPORT <port> FUNNEL1.ATBSource ETM <port> (1) ETMTPIUFUNNELPORT <port> FUNNEL3.ATBSource ETM <port> (1) FILLDRZERO [ON | OFF] CHIPDRPRE 0 CHIPDRPOST 0 CHIPDRLENGTH <bits_of_complete_dr_path> CHIPDRPATTERN.Alternate 0 FUNNEL2BASE <address> FUNNEL2.Base <address> FUNNELBASE <address> FUNNEL1.Base <address> HSMBASE <address> HSM.Base <address> 1989-2023 © Lauterbach C2000 Debugger...
  • Page 44 OCP.Base <address> TIOCPTYPE <type> OCP.Type <type> TIPMIBASE <address> PMI.Base <address> TISCBASE <address> SC.Base <address> TISTMBASE <address> STM1.Base <address> STM1.Mode STP STM1.Type TI TPIUBASE <address> TPIU.Base <address> TPIUFUNNELBASE <address> FUNNEL3.Base <address> TRACEETBFUNNELPORT <port> FUNNEL4.ATBSource ADTF <port> (1) 1989-2023 © Lauterbach C2000 Debugger...

  • Page 45: System.config.erad

    Defines the base address of the ERAD module. RESet Resets ERAD settings. view Displays ERAD settings. SYStem.CPU Select the used CPU Format: SYStem.CPU <cpu> <cpu>: C280X | C2808 | … Default selection: C280X. Selects the processor type. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 46: System.jtagclock

    (Compensation by RTCK). This feature requires that the target provides an RTCK signal. In contrast to the RTCK option, the TCK is always output with the selected, fixed frequency. SYStem.JtagClock CRTCK 1989-2023 © Lauterbach C2000 Debugger...

  • Page 47: System.lock

    SYStem.CONFIG TCKLevel must be set properly. They define the TAP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 48: System.memaccess

    Program execution can be stopped by the break command or external trigger. NoDebug Resets the target with debug mode disabled. In this mode no debugging is possible. The CPU state keeps in the state of NoDebug. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 49: System.option.ahbhprot

    Default: OFF. Enables ACE transactions on the DAP AXI-AP, including barriers. This does only work if the debug logic of the target CPU implements coherent AXI accesses. Otherwise this option will be without effect. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 50: System.option.axicacheflags

    SYStem.Option.AXIHPROT <value> (deprecated) SYStem.CONFIG.AXIAPn.HPROT instead. Default: 0 This option selects the value used for the HPROT bits in the Control Status Word (CSW) of a CoreSight AXI Access Port, when using the AXI: memory class. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 51: System.option.dapdbgpwrupreq

    Bug fix for derivatives which do not return the correct pattern on a DAP (Arm CoreSight Debug Access Port) instruction register (IR) scan. When activated, the returned pattern will not be checked by the debugger. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 52: System.option.dapremap

    The system power is released at the end of the debug session, and the control bit is set to 0. System power is not requested by the debugger on a debug session start, and the control bit is set to 0. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 53: System.option.debugportoptions

    Use nTRST the same way as in JTAG mode which is typically a low-pulse on debugger start-up followed by keeping it high. Keep nTRST low during serial wire operation. HIGH Keep nTRST high during serial wire operation 1989-2023 © Lauterbach C2000 Debugger...

  • Page 54: System.option.executionmode

    If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 55: System.option.targetserver

    If possible (nRESET is open collector), this command asserts the nRESET line on the debug connector. This will reset the target including the CPU but not the debug port. The function only works when the system is in SYStem.Mode.Up. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 56: Tronchip Commands

    TrOnchip Commands TrOnchip.state Display on-chip trigger window Format: TrOnchip.state Opens the TrOnchip.state window. TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 57: Erad Commands

    Format: ERAD.ON Turns on the ERAD module features on if they were turned off before (see ERAD.OFF). Usually the ERAD is automatically turned on if available and does not need to be turned on manually. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 58: Jtag Connection

    JTAG Connection Mechanical Description of the 20-pin Debug Cable This connector is defined by ARM. LAUTERBACH’s debugger JTAG Debugger for ARM7 (LA-7746) and JTAG Debugger for ARM9 (LA-7742) and JTAG Debugger for TMS320 are supplied with this connector: Signal Signal...

  • Page 59: Electrical Description Of The 20-Pin Debug Cable

    JTAG connector is tristated by the debugger and it is pulled low otherwise. This signal is normally not required, but can be used to detect the tristate state if more than one debug tools are connected to the same JTAG port. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 60: Mechanical Description Of The Ti Connector

    Mechanical Description of the TI Connector Please refer to https://support.lauterbach.com/kb. 1989-2023 © Lauterbach C2000 Debugger...

  • Page 61: Operation Voltage

    Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for C2000 DSP (ICD) LA-7847 1.8 .. 3.6 V 1989-2023 © Lauterbach C2000 Debugger...

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